Abstract: The present invention provides a method of planarizing a surface on a semiconductor wafer containing metal. In one embodiment, the method comprises selecting a slurry that contains conventional components of an abrasive and an oxidant. The oxidant is known to have a known rate of oxidation and is capable of oxidizing the metal. This embodiment further comprises reducing a rate of exposure of the metal to the oxidant by altering a property of the slurry, oxidizing the metal at the reduced rate to form an oxide of the metal, and removing the oxide with the abrasive to produce a planarized surface of the semiconductor wafer.

Abstract: A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate.This invention was made with Government support under contract No. F29601-87-R-0202 awarded by the Defense Advanced Research Projects Agency, and under contract No. F33615-84-C-1570 awarded by the Air Force Wright Aeronautical Laboratories. The Government has certain rights in this invention.

Abstract: The area of a surface-emitting LED is reduced, and hence the number of LEDs which can be obtained from a single wafer is increased, by a chip design in which the light-emitting spot is positioned asymmetrically toward one corner of the chip. Preferably, an L-shaped contact is formed on the light output surface so that light-emitting spot emerges from between the legs of the L.

Abstract: An etching process is described which can etch geometrical shapes on the surface of an n-type or intrinsic compound semiconductor and yield surfaces of optical quality without further processing. The etching process is an electrochemical process where etching is proportional to light intensity. The process involves applying a potential to the compound semiconductor while immersed in an electrolytic solution and irradiating the surface to be etched with light in a certain energy range. The electrolytic solution contains hydrofluoric acid. The distribution of light intensity and ray direction is selected to produce the desired geometrical shape. Particularly advantageous is that the surfaces produced are of optical quality. For example, lenses produced by the etching process exhibit surfaces of optical quality. Further, the process can be carried out on all the lenses on a wafer simultaneously without attention to individual devices. This is highly desirable economically.