Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.

Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.

Abstract: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Abstract: Disclosed is a processor having a normal execution mode and a host execution mode. A virtual machine monitor (VMM) operable in conjunction with the host execution mode creates at least one protected mode environment to operate guest software in a protected memory area. Responsive to a command to switch between protected modes, the VMM causes the processor to atomically switch between an original protected mode environment and a target protected mode environment. A virtual machine execution (VMX) mode may be utilized to enable virtual machine functionality for use in switching between protected modes.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Abstract: A multiple, cooperating operating systems (OS) platform system with multi processors. Multiple operating systems, each of which may be of a different type or nature, can run on different partitions of the multi-processor platform and yet coexist and cooperate. A real time operating system (RTOS) executing on a processor can communicate with another OS executing on another processor via a portion of memory accessible by the RTOS and the OS by perform read and write operations.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Abstract: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop.

Abstract: A multiple, cooperating operating systems (OS) platform system with multi processors. Multiple operating systems, each of which may be of a different type or nature, can run on different partitions of the multi-processor platform and yet coexist and cooperate. A real time operating system (RTOS) executing on a processor can communicate with another OS executing on another processor via a portion of memory accessible by the RTOS and the OS by perform read and write operations.

Abstract: Embodiments of a multi-processor platform including multiple, cooperating operating systems are described. Multiple operating systems, each of which may be of a different type or nature, run on different partitions of the multi-processor platform, yet coexist and cooperate. In various embodiments, different specialized operating systems, suitable for particular tasks, run on different partitions of the platform. In one embodiment, a host operating system, using a driver, boots and partitions a portion of the platform running other operating systems, and then communicates with, and shares work with, the other operating systems. In one embodiment, the multi-processor platform includes a host operating system and multiple specialized operating systems, such as real-time operating systems, operating alongside the host operating system. Other embodiments are described and claimed.

Abstract: Disclosed is a processor having a normal execution mode and a secure execution mode to create a secure execution environment. A secure virtual machine monitor (SVMM) implements the secure execution environment in which a plurality of separate virtual machines are created that operate simultaneously and separately from one another including at least a first virtual machine to implement trusted guest software in a protected memory area and a second virtual machine to implement a non-trusted guest operating system (OS) simultaneously in a non-protected memory area. Responsive to a command to tear down the secure execution environment, the SVMM causes the processor to exit out of the secure execution mode, tears down the secure execution environment, and instructs the non-trusted guest OS to resume control in the normal execution mode.

Abstract: System and method for binding virtual machines to hardware contexts. A method includes obtaining resource requirements for a plurality of virtual machines, and binding one or more of the plurality of virtual machines to one or more of a plurality of hardware contexts associated with a processor based upon the resource requirements. The resource requirements may be the bandwidth and latency of the virtual machines. The method may be implemented as software on a storage device on a computing device having a processor that supports multiple hardware contexts. The method is particularly beneficial for real-time virtual machines.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A method for assigning a device to a first virtual machine includes connecting the device, directly or indirectly, to a computer through an interconnect. The first virtual machine and a second virtual machine are run on the computer. The device is assigned to the first virtual machine for exclusive use by the first virtual machine, and the assignment is enforced.

Abstract: A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Abstract: System and method for binding virtual machines to hardware contexts. A method includes obtaining resource requirements for a plurality of virtual machines, and binding one or more of the plurality of virtual machines to one or more of a plurality of hardware contexts associated with a processor based upon the resource requirements. The resource requirements may be the bandwidth and latency of the virtual machines. The method may be implemented as software on a storage device on a computing device having a processor that supports multiple hardware contexts. The method is particularly beneficial for real-time virtual machines.

Abstract: A method for assigning a device to a first virtual machine includes connecting the device, directly or indirectly, to a computer through an interconnect. The first virtual machine and a second virtual machine are run on the computer. The device is assigned to the first virtual machine for exclusive use by the first virtual machine, and the assignment is enforced.

Abstract: A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.