Abstract: The present disclosure relates to semiconductor manufacturing and the teachings of the present disclosure may be embodied in a semiconductor chip with an interconnect monitor. Some embodiments may include arrays of diodes on the semiconductor chip; each diode with a stack of vertical interconnects and metal contacts, the stack and the diode connected in series and control mechanisms for addressing the diodes. The control mechanisms may include first inverters for applying either a high or a low voltage to columns of the diode stacks, connected at one end of each diode stack.

Abstract: The present disclosure teaches a method for manufacturing a module comprising an integrated circuit and a sensor. The method may comprise: mounting an integrated circuit (IC) die on a printed circuit board (PCB) using a high temperature process to provide an electrical connection between interconnects of the PCB and the die; and printing a sensor directly onto the module after all high temperature mounting processes are complete.

Abstract: The present disclosure relates to semiconductor manufacturing and the teachings of the present disclosure may be embodied in a semiconductor chip with an interconnect monitor. Some embodiments may include arrays of diodes on the semiconductor chip; each diode with a stack of vertical interconnects and metal contacts, the stack and the diode connected in series and control mechanisms for addressing the diodes. The control mechanisms may include first inverters for applying either a high or a low voltage to columns of the diode stacks, connected at one end of each diode stack.

Abstract: The present disclosure teaches a method for manufacturing a module comprising an integrated circuit and a sensor. The method may comprise: mounting an integrated circuit (IC) die on a printed circuit board (PCB) using a high temperature process to provide an electrical connection between interconnects of the PCB and the die; and printing a sensor directly onto the module after all high temperature mounting processes are complete.

Abstract: A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first conductivity type on said substrate; first and second base regions of the second conductivity type within said epitaxial layer, spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged in said first and second base regions, respectively, wherein said first and second base region is operable to form first and second lateral channels between said source region and said epitaxial layer; a gate structure insulated from said epitaxial layer by an insulation layer and arranged above the region between the first and second base regions and wherein the gate structure comprises first and second gate regions, each gate region only covering the first and second channel, respectively within said first and second base region.

Abstract: Laser target practice using an ultra-violet light emitting laser that is pulsed on when a weapon trigger is pulled. The LTV laser light pulse illuminates a spot on a target having a phosphorus coating on a face thereof. The phosphorus within the illuminated spot glows for a certain time thereby visually indicating a location of the spot on the target. The UV laser light pulse may also illuminate a spot on a target having a photochromic paint coatings on a face thereof. The photochromic paint coatings within the illuminated spot changes color thereby indicating a location of the spot on the target.

Abstract: A method for producing a power field effect transistor (FET) device having a low series resistance between the drain and source when switched on has the steps of: forming a vertical power FET in a semiconductor die; and back-grinding the semiconductor die to a thickness of less than or equal to about 100 ?m (4 mils) or less.

Abstract: A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first conductivity type on said substrate; first and second base regions of the second conductivity type within said epitaxial layer, spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged in said first and second base regions, respectively, wherein said first and second base region is operable to form first and second lateral channels between said source region and said epitaxial layer; a gate structure insulated from said epitaxial layer by an insulation layer and arranged above the region between the first and second base regions and wherein the gate structure comprises first and second gate regions, each gate region only covering the first and second channel, respectively within said first and second base region.

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g.

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g.

Abstract: An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N? well is located substantially under the N+ and P+ diffusions.

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g.

Abstract: A bistable memory device changes logic state each time an event occurs. The bistable memory device has an logic output coupled to a digital processor input. The digital processor reads the logic state of the bistable memory device from its logic output and compares the logic state read to a stored previous logic state obtained from a previous read. If the logic state read and the stored previous logic state are the same, then no event has occurred during the time between the read and previous read of the logic states of the bistable memory device. If different, then an event has occurred during the time between the read and previous read of the logic states of the bistable memory device. The event detection may be used in combination with a digital system communicating by serial digital data transmissions.

Abstract: A matching capacitor array is implemented on a single, monolithic integrated circuit. The array features a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Abstract: A bistable memory device changes logic state each time an event occurs. The bistable memory device has an logic output coupled to a digital processor input. The digital processor reads the logic state of the bistable memory device from its logic output and compares the logic state read to a stored previous logic state obtained from a previous read. If the logic state read and the stored previous logic state are the same, then no event has occurred during the time between the read and previous read of the logic states of the bistable memory device. If different, then an event has occurred during the time between the read and previous read of the logic states of the bistable memory device. The event detection may be used in combination with a digital system communicating by serial digital data transmissions.

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Abstract: A system for allowing a two word jump instruction to be executed in the same number of cycles as a single word jump instruction, thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus.

Abstract: A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on a page of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables that are located on a pre-defined page of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in a page select register currently being used by the microcontroller.

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.