Abstract: A method of forming a MEMS device includes providing a substrate having a device stopper. The device stopper is integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may be formed in the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be formed over the thermal dielectric isolation layer and the device cavity.

Abstract: In a non-limiting embodiment, a device may include a substrate, and a hybrid active structure disposed over the substrate. The hybrid active structure may include an anchor region and a free region. The hybrid active structure may be connected to the substrate at least at the anchor region. The anchor region may include at least a segment of a piezoelectric stack portion. The piezoelectric stack portion may include a first electrode layer, a piezoelectric layer over the first electrode layer, and a second electrode layer over the piezoelectric layer. The free region may include at least a segment of a mechanical portion. The piezoelectric stack portion may overlap the mechanical portion at edges of the piezoelectric stack portion.

Abstract: A method of forming a MEMS device includes providing a substrate having a device stopper. The device stopper is integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may be formed in the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be formed over the thermal dielectric isolation layer and the device cavity.

Abstract: In a non-limiting embodiment, a MEMS device may include a substrate having a device stopper. The device stopper may be integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may extend through the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be arranged over the thermal dielectric isolation layer and the device cavity.

Abstract: In a non-limiting embodiment, a MEMS device may include a substrate having a device stopper. The device stopper may be integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may extend through the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be arranged over the thermal dielectric isolation layer and the device cavity.

Abstract: In a non-limiting embodiment, a device may include a substrate, and a hybrid active structure disposed over the substrate. The hybrid active structure may include an anchor region and a free region. The hybrid active structure may be connected to the substrate at least at the anchor region. The anchor region may include at least a segment of a piezoelectric stack portion. The piezoelectric stack portion may include a first electrode layer, a piezoelectric layer over the first electrode layer, and a second electrode layer over the piezoelectric layer. The free region may include at least a segment of a mechanical portion. The piezoelectric stack portion may overlap the mechanical portion at edges of the piezoelectric stack portion.

Abstract: The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).

Abstract: The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).

Abstract: A wafer bonding layer and a process for using the same for bonding wafers are presented. The wafer bonding process includes providing a first wafer, providing a second type wafer and providing a water bonding layer. The wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film and passive or active device structures are formed on the conductive layer within the openings. The substrate is bonded to the sacrificial wafer wherein the thin film and passive or active device structures and the photoresist layer provide the bonding and wherein the thin film and passive or active device structures contact the substrate at the target transfer regions. The photoresist is stripped in a high frequency agitation bath wherein the photoresist separates from the sacrificial wafer and wherein the thin film and passive or active device structures separate from the polymer layer to complete transfer bonding.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: This invention describes a method of stacking, bonding, and electrically interconnecting a plurality of thin integrated circuit wafers to form an interconnected stack of integrated circuit layers. The first integrated circuit layer is formed by conventional processing on a silicon wafer to the stage where bond pads are patterned on a wiring layer interconnecting the subjacent semiconductive devices. The remaining integrated circuit layers are formed by first processing a standard wafer to form integrated circuit devices and wiring levels up to but not including bond pads. Each of these wafers is mounted onto a handler wafer by its upper face with a sacrificial bonding agent. The wafer is thinned, permanently fastened to the top surface of the first base wafer by a non-conductive adhesive applied to the thinned under face, and dismounted from the handler. Vertical openings are etched through the thinned layer to the bond pads on the subjacent wafer.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film and passive or active device structures are formed on the conductive layer within the openings. The substrate is bonded to the sacrificial wafer wherein the thin film and passive or active device structures and the photoresist layer provide the bonding and wherein the thin film and passive or active device structures contact the substrate at the target transfer regions. The photoresist is stripped in a high frequency agitation bath wherein the photoresist separates from the sacrificial wafer and wherein the thin film and passive or active device structures separate from the polymer layer to complete transfer bonding.

Abstract: A new method to form shielded vias with microstrip ground plane in the manufacture of an integrated circuit device is achieved. The method comprises, first, providing a substrate. The substrate is etched through to form holes for planned shielded vias with microstrip ground plane. A first dielectric layer is formed overlying the top side of the substrate and lining the holes. A first conductive layer is deposited overlying the first dielectric layer and lining the holes. A second dielectric layer is deposited overlying the first conductive layer and lining the holes. A second conductive layer is deposited overlying the second dielectric layer and filling the holes. The second conductive layer is planarized to confine the second conductive layer to the holes and to thereby complete the shielded vias with microstrip ground plane. Silicon carrier modules and stacked, multiple integrated circuit modules are formed using shielded vias with microstrip ground plane to improve RF performance.

Abstract: A wafer is provided having through-holes therein to form a through-hole via wafer. A substrate of a sacrificial wafer is provided. The substrate is coated with a polymer having low adhesion to metals. A conductive layer is deposited on the polymer. A photoresist layer is coated on the conductive layer. The through-hole via wafer is bonded to the sacrificial wafer wherein the photoresist layer provides the bonding. The photoresist exposed in the through-holes is developed away to expose the conductive layer. The through-holes are filled with a conductive material by electroplating the conductive layer. The photoresist is stripped in an ultrasonic bath wherein the photoresist separates from the through-hole wafer and wherein the filled through-holes separate from the polymer at an interface between the polymer and the conductive layer to complete separation of the through-hole via wafer from the sacrificial wafer.

Abstract: A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.