Patents by Inventor Ranjeet Alexis

Ranjeet Alexis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6260103
    Abstract: A read-while-write memory device. The read-while-write memory device includes a read memory plane and a write memory plane. A first number of read sense amplifiers greater than one is coupled in parallel to the read memory plane in response to a memory read operation. A second number of verify sense amplifiers greater than zero and less than the first number is coupled to the write memory plane in response to one of a memory write or erase operation.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: July 10, 2001
    Assignee: Intel Corporation
    Inventors: Ranjeet Alexis, Robert E. Larsen
  • Patent number: 6182189
    Abstract: An interface for a read-while-write memory. A memory device includes a single-chip memory array and an interface that is responsive to one or more commands to configure the memory array in a read-while-write configuration.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: January 30, 2001
    Assignee: Intel Corporation
    Inventors: Ranjeet Alexis, Peter K. Hazen, Charles W. Brown, Robert E. Larsen
  • Patent number: 6088264
    Abstract: A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: July 11, 2000
    Assignee: Intel Corporation
    Inventors: Peter K. Hazen, Ranjeet Alexis, Robert E. Larsen, Charles W. Brown, Sanjay Talreja
  • Patent number: 5933026
    Abstract: A low-power interface for nonvolatile writeable memory is described. The interface includes an input buffer and an output buffer. The input buffer receives input signals having one of a number of pairs of logic levels. The input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply as the nonvolatile writeable memory. The input buffer translates the input signals received to the signal level used by the nonvolatile writeable memory. The output buffer is coupled to the nonvolatile writeable memory and is coupled to a different power supply from the input buffer and the nonvolatile writeable memory. The output buffer translates the signals received from the nonvolatile writeable memory to the same signal levels as the input signal. The input buffer and output buffer utilize input/output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: August 3, 1999
    Assignee: Intel Corporation
    Inventors: Robert E. Larsen, Harry Q. Pon, Sanjay Talreja, Marcus E. Landgraf, Ranjeet Alexis
  • Patent number: 5864231
    Abstract: A self-compensating current mirroring circuit including first and second transistor devices respectively joined in the path of a current to be mirrored and the path of a mirrored current, the first transistor device being in circuit with a compensating transistor device, the sizes of the first and second transistor devices being such that the currents through the first and second transistor devices are maintained at identical levels during operation.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: January 26, 1999
    Assignee: Intel Corporation
    Inventor: Ranjeet Alexis
  • Patent number: 5835927
    Abstract: A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: November 10, 1998
    Assignee: Intel Corporation
    Inventors: Mickey L. Fandrich, Salim B. Fedel, Ranjeet Alexis, Mamun Rashid
  • Patent number: 5748939
    Abstract: A memory device includes a cell array having a plurality of memory cells and a read/write circuit having circuitry for selecting, writing, and reading the memory cells according to a plurality of control signals. A control register circuit is provided that has at least one control register coupled to communicate over a central control bus. A control access circuit is provided that receives an access request targeted for the control register, and translates the access request into an access cycle on the central control bus. The access cycle loads the control register and causes the control register circuit to generate the control signals. The control access circuit receives the access request targeted for the control register from an array controller circuit that generates the access request to load the control register and generate the control signals according to a user command received over a host bus.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: May 5, 1998
    Assignee: Intel Corporation
    Inventors: Rodney R. Rozman, Richard J. Durante, Mickey L. Fandrich, Ranjeet Alexis
  • Patent number: 5640083
    Abstract: A circuit for rapidly raising the value of voltage at a circuit node to a predetermined precise level including first and second charging circuits, and circuitry including a timing circuit responsive to an enabling signal for connecting the one of the charging circuits to the circuit node for a first limited period and then connecting the other of the charging circuits to the circuit node thereafter.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: June 17, 1997
    Assignee: Intel Corporation
    Inventor: Ranjeet Alexis
  • Patent number: 5623620
    Abstract: A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: April 22, 1997
    Assignee: Intel Corporation
    Inventors: Mickey L. Fandrich, Salim B. Fedel, Ranjeet Alexis, Mamun Rashid
  • Patent number: 5621686
    Abstract: A current mirroring circuit including first and second field effect transistor devices connected in a current mirroring arrangement, a circuit for summing a first plurality of identical currents to provide current for the first field effect transistor device, a circuit for dividing the current from the second field effect transistor device into a second plurality of identical currents, and an output circuit connected to mirror any one of the second plurality of identical currents.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 15, 1997
    Assignee: Intel Corporation
    Inventor: Ranjeet Alexis