Patents by Inventor Raul A. Garibay

Raul A. Garibay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10719651
    Abstract: A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 21, 2020
    Assignee: ARTERIS, INC.
    Inventors: Raul A. Garibay, Jr., Manadher Kharroubi
  • Publication number: 20200192858
    Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 18, 2020
    Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
  • Patent number: 10606797
    Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 31, 2020
    Assignee: Mythic, Inc.
    Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
  • Publication number: 20200012617
    Abstract: Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 9, 2020
    Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
  • Publication number: 20200012616
    Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 9, 2020
    Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
  • Patent number: 10521395
    Abstract: Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 31, 2019
    Assignee: Mythic, Inc.
    Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
  • Publication number: 20190205493
    Abstract: A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Applicant: Arteris, Inc.
    Inventors: Raul A. GARIBAY, Manadher KHARROUBI
  • Publication number: 20110208950
    Abstract: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.
    Type: Application
    Filed: March 21, 2011
    Publication date: August 25, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thang Minh Tran, Raul A. Garibay, JR., James Nolan Hardage
  • Patent number: 7900075
    Abstract: A pipelined computer system with power management control in accordance with one or both of a power management signal and a power management instruction.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Patent number: 7900076
    Abstract: A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Patent number: 7509512
    Abstract: An instruction-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to an instruction executed by the pipeline subcircuitry.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: March 24, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Publication number: 20080109667
    Abstract: A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.
    Type: Application
    Filed: October 31, 2007
    Publication date: May 8, 2008
    Applicant: National Semiconductor Corporation
    Inventors: Robert Maher, Raul Garibay, Margaret Herubin, Mark Bluhm
  • Publication number: 20080098248
    Abstract: A pipelined computer system with power management control in accordance with one or both of a power management signal and a power management instruction.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 24, 2008
    Applicant: National Semiconductor Corporation
    Inventors: Robert Maher, Raul Garibay, Margaret Herubin, Mark Bluhm
  • Patent number: 7237065
    Abstract: A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: June 26, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Thang M. Tran, Raul A. Garibay, Jr., Muralidharan S. Chinnakonda, Paul K. Miller
  • Publication number: 20070028051
    Abstract: The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.
    Type: Application
    Filed: August 1, 2005
    Publication date: February 1, 2007
    Applicants: ARM Limited, Texas Instruments Incorporated
    Inventors: Barry Williamson, Gerard Williams, Muralidharan Chinnakonda, Raul Garibay
  • Publication number: 20060271738
    Abstract: A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.
    Type: Application
    Filed: May 24, 2005
    Publication date: November 30, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Thang Tran, Raul Garibay, Muralidharan Chinnakonda, Paul Miller
  • Patent number: 7120810
    Abstract: An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: October 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Patent number: 7062666
    Abstract: A signal-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to at least one control signal.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: June 13, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Publication number: 20060095732
    Abstract: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.
    Type: Application
    Filed: May 18, 2005
    Publication date: May 4, 2006
    Inventors: Thang Tran, Raul Garibay, James Hardage
  • Publication number: 20060085707
    Abstract: A system comprising a tester and an integrated circuit, where the integrated circuit comprises a flip-flop, the flip-flop coupled to the tester and a circuit logic. The flip-flop comprises a scan input signal and a scan output signal, the signals coupled to the tester. The flip-flop also comprises multiple clock input signals.
    Type: Application
    Filed: September 28, 2004
    Publication date: April 20, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Waheed Khan, Raul Garibay, Denzil Fernandes