Patents by Inventor Ravi Gutala

Ravi Gutala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964624
    Abstract: A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through channels in the fluid routing device to absorb heat generated by first and second integrated circuit dies in the integrated circuit package. The fluid routing device is mounted on a surface of each of the first and second integrated circuit dies. The fluid coolant is provided from the channels to a fluid outlet of the fluid routing device. A flow of the fluid coolant through the fluid routing device is adjusted to reduce a temperature of the first integrated circuit die in response to an increase in a workload of the first integrated circuit die.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Gutala, Aravind Dasu
  • Patent number: 10770372
    Abstract: A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel directly contacts an apparatus attached to a bottom of the fluid routing device. The second vertical channel is open to the horizontal channel. The second vertical channel is oriented to provide fluid coolant vertically up away from the horizontal channel. The fluid outlet is open to the second vertical channel such that fluid coolant from the second vertical channel exits the fluid routing device through the fluid outlet.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 8, 2020
    Assignee: Altera Corporation
    Inventors: Ravi Gutala, Arif Rahman, Aravind Dasu, Thomas Sarvey, Devdatta Kulkarni
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Patent number: 10504819
    Abstract: An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second sub-channels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: December 10, 2019
    Assignee: Altera Corporation
    Inventors: Ravi Gutala, Arifur Rahman, Karthik Chandrasekar
  • Publication number: 20190012116
    Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Ravi Gutala, Aravind Dasu
  • Publication number: 20180211900
    Abstract: A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through channels in the fluid routing device to absorb heat generated by first and second integrated circuit dies in the integrated circuit package. The fluid routing device is mounted on a surface of each of the first and second integrated circuit dies. The fluid coolant is provided from the channels to a fluid outlet of the fluid routing device. A flow of the fluid coolant through the fluid routing device is adjusted to reduce a temperature of the first integrated circuit die in response to an increase in a workload of the first integrated circuit die.
    Type: Application
    Filed: January 26, 2017
    Publication date: July 26, 2018
    Applicant: Intel Corporation
    Inventors: Ravi Gutala, Aravind Dasu
  • Publication number: 20180090417
    Abstract: A fluid routing device includes a fluid inlet, first vertical channels, a horizontal channel, a second vertical channel, and a fluid outlet. The first vertical channels are open to the fluid inlet. The horizontal channel is open to each of the first vertical channels. The first vertical channels are oriented to provide fluid coolant from the fluid inlet vertically down to the horizontal channel. The horizontal channel is open on one side such that fluid coolant in the horizontal channel directly contacts an apparatus attached to a bottom of the fluid routing device. The second vertical channel is open to the horizontal channel. The second vertical channel is oriented to provide fluid coolant vertically up away from the horizontal channel. The fluid outlet is open to the second vertical channel such that fluid coolant from the second vertical channel exits the fluid routing device through the fluid outlet.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Applicant: Altera Corporation
    Inventors: Ravi Gutala, Arif Rahman, Aravind Dasu, Thomas Sarvey, Devdatta Kulkarni
  • Publication number: 20170133298
    Abstract: An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second sub-channels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region.
    Type: Application
    Filed: November 11, 2015
    Publication date: May 11, 2017
    Applicant: Altera Corporation
    Inventors: Ravi Gutala, Arifur Rahman, Karthik Chandrasekar
  • Patent number: 8301977
    Abstract: In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 30, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Meenatchi Jagasivmani, Anthony Ko, Rich E. Fackenthal, Ferdinando Bedeschi, Enzo Donze, Ravi Gutala
  • Publication number: 20100169740
    Abstract: In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Applicant: STMicroelectronics S.r.I.
    Inventors: Meenatchi Jagasivamani, Anthony Ko, Rich E. Fackenthal, Ferdinando Bedeschi, Enzo Donze, Ravi Gutala
  • Patent number: 6009014
    Abstract: The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: December 28, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shane C. Hollmer, Chung-You Hu, Binh Q. Le, Pau-ling Chen, Jonathan Su, Ravi Gutala, Colin Bill
  • Patent number: 5754475
    Abstract: An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: May 19, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Colin Bill, Ravi Gutala, Qimeng (Derek) Zhou, Jonathan Su