Patents by Inventor Ravi Keshav Joshi

Ravi Keshav Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200013723
    Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 9, 2020
    Inventors: Edward Fuergut, Ravi Keshav Joshi, Ralf Siemieniec, Thomas Basler, Martin Gruber, Jochen Hilsenbeck, Dethard Peters, Roland Rupp, Wolfgang Scholz
  • Publication number: 20200013722
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Müller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Publication number: 20190355819
    Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
  • Patent number: 10475743
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Publication number: 20190333765
    Abstract: A method for manufacturing a high-voltage semiconductor device includes exposing a semiconductor substrate to a plasma to form a protective substance layer on the semiconductor substrate. A semiconductor device includes a semiconductor substrate and a protective substance layer on the semiconductor substrate.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 31, 2019
    Inventors: Markus Kahn, Oliver Humbel, Ravi Keshav Joshi, Philipp Sebastian Koch, Angelika Koprowski, Bernhard Leitl, Christian Maier, Gerhard Schmidt, Juergen Steinbrenner
  • Publication number: 20190311966
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 10347491
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Patent number: 10256097
    Abstract: A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Romain Esteve, Roland Rupp, Francisco Javier Santos Rodriguez, Gerald Unegg
  • Patent number: 10121859
    Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 6, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Oliver Blank, Oliver Hellmund, Martin Poelzl
  • Publication number: 20180247820
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Keshav Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Patent number: 10049879
    Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Romain Esteve, Markus Kahn, Kurt Pekoll, Juergen Steinbrenner, Gerald Unegg
  • Publication number: 20180182629
    Abstract: Disclosed is a method. The method includes implanting recombination center particles into a semiconductor body via at least one contact hole in an insulation layer formed on top of the semiconductor body, forming a contact electrode electrically connected to the semiconductor body in the at least one contact hole, and annealing the semiconductor body to diffuse the recombination center particles in the semiconductor body. Forming the contact electrode includes forming a barrier layer on sections of the semiconductor body uncovered in the at least one contact hole, wherein the barrier layer is configured to inhibit the recombination center particles from diffusing out of the semiconductor body.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 28, 2018
    Inventors: Wolfgang Jantscher, Alexander Binter, Oliver Blank, Petra Fischer, Ravi Keshav Joshi, Kurt Pekoll, Manfred Pippan, Andreas Riegler, Werner Schustereder, Juergen Steinbrenner, Waqas Mumtaz Syed
  • Publication number: 20180174840
    Abstract: A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 21, 2018
    Inventors: Ravi Keshav Joshi, Romain Esteve, Roland Rupp, Francisco Javier Santos Rodriguez, Gerald Unegg
  • Publication number: 20180076036
    Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.
    Type: Application
    Filed: May 1, 2017
    Publication date: March 15, 2018
    Inventors: Ravi Keshav Joshi, Romain Esteve, Markus Kahn, Kurt Pekoll, Juergen Steinbrenner, Gerald Unegg
  • Patent number: 9917333
    Abstract: A lithium ion battery includes a first substrate having a first main surface, and a lid including an insulating material. The lid is attached to the first main surface of the first substrate, and a cavity is defined between the first substrate and the lid. The lithium ion battery further includes an electrical interconnection element in the lid, the electrical interconnection element providing an electrical connection between a first main surface and a second main surface of the lid. The lithium ion battery further includes an electrolyte in the cavity, an anode at the first substrate, the anode including a component made of a semiconductor material, and a cathode at the lid.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 13, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Vijaye Kumar Rajaraman, Kamil Karlovsky, Thomas Neidhart, Karl Mayer, Rainer Leuschner, Christine Moser, Ravi Keshav Joshi, Alexander Breymesser, Bernhard Goller, Francisco Javier Santos Rodriguez, Peter Zorn
  • Publication number: 20180061660
    Abstract: A method of fabricating a semiconductor device includes forming a barrier layer over a surface of a semiconductor substrate. A treated barrier layer is formed by subjecting an exposed surface of the barrier layer to a surface treatment process. The surface treatment process includes treating the surface with a reactive material. A material layer is formed over the treated barrier layer. The material layer comprises a metal.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 1, 2018
    Inventors: Ravi Keshav Joshi, Kae-Horng Wang, Stefan Willkofer
  • Patent number: 9773736
    Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 26, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Juergen Steinbrenner, Christian Fachmann, Petra Fischer, Roman Roth
  • Publication number: 20170271268
    Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.
    Type: Application
    Filed: March 14, 2017
    Publication date: September 21, 2017
    Inventors: Frank Hille, Ravi Keshav Joshi, Michael Fugger, Oliver Humbel, Thomas Laska, Matthias Mueller, Roman Roth, Carsten Schaeffer, Hans-Joachim Schulze, Holger Schulze, Juergen Steinbrenner, Frank Umbach
  • Publication number: 20170271446
    Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 21, 2017
    Inventors: Ravi Keshav Joshi, Johannes Baumgartl, Oliver Blank, Oliver Hellmund, Martin Poelzl
  • Patent number: 9666482
    Abstract: A silicon-carbide substrate that includes a doped contact region and a dielectric layer is provided. A protective layer is formed on the dielectric layer. A structured mask is formed on the protective layer. Sections of the protective layer and the dielectric layer that are exposed by openings in the mask are removed. The structured mask is removed. A metal layer is deposited such that a first portion of the metal layer directly contacts the doped contact region and a second portion of the metal layer lines the remaining sections of the protective layer and the dielectric layer. A first rapid thermal anneal process is performed. After performing the first rapid thermal anneal process, the second portion of the metal layer and the remaining section of the protective layer are removed without removing the first portion of the metal layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 30, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ravi Keshav Joshi, Romain Esteve, Markus Kahn, Kurt Pekoll, Juergen Steinbrenner, Gerald Unegg