Patents by Inventor Ravi Prakash Gutala

Ravi Prakash Gutala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190230049
    Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Kevin Clark, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Publication number: 20190140648
    Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Kevin Clark, Scott J. Weber, James Ball, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Publication number: 20190131976
    Abstract: A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Karthik Chandrasekar, Guang Chen, Wendemagegnehu T. Beyene, Ravi Prakash Gutala
  • Publication number: 20190103872
    Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 4, 2019
    Inventors: Kevin Clark, Scott J. Weber, James Ball, Simon Chong, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Publication number: 20190042251
    Abstract: An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Inventors: Eriko Nurvitadhi, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Publication number: 20190042127
    Abstract: An integrated circuit device may cache configuration data to enable rapid configuration from fabric cache memory. The integrated circuit device may include programmable logic fabric having configuration memory and programmable logic elements controlled by the configuration memory, and sector-aligned memory apart from the programmable logic fabric. A first sector of the configuration memory may be programmed with first configuration data. The sector-aligned memory may include a first sector of sector-aligned memory that may cache the first configuration data while the configuration memory is programmed with the first configuration data a first time. A second sector of sector-aligned memory may cache second configuration data for a second sector of the configuration memory in parallel while the first sector of sector-aligned memory caches the first configuration data for the first sector of the configuration memory.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Inventors: Scott J. Weber, David Greenhill, Sean R. Atsatt, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan
  • Publication number: 20190044515
    Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.
    Type: Application
    Filed: December 27, 2017
    Publication date: February 7, 2019
    Inventors: Ravi Prakash Gutala, Aravind Raghavendra Dasu, Sean R. Atsatt, Scott J. Weber
  • Publication number: 20190041923
    Abstract: An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.
    Type: Application
    Filed: December 27, 2017
    Publication date: February 7, 2019
    Inventors: Sean R. Atsatt, Scott J. Weber, Aravind Raghavendra Dasu, Ravi Prakash Gutala
  • Publication number: 20190043536
    Abstract: An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Inventors: Scott J. Weber, Sean R. Atsatt, Ravi Prakash Gutala, Aravind Raghavendra Dasu, Jun Pin Tan
  • Publication number: 20190044519
    Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.
    Type: Application
    Filed: June 27, 2018
    Publication date: February 7, 2019
    Inventors: Sean R. Atsatt, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Publication number: 20190042529
    Abstract: Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Inventors: Eriko Nurvitadhi, Scott J. Weber, Ravi Prakash Gutala, Aravind Raghavendra Dasu
  • Patent number: 6275415
    Abstract: A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: August 14, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sameer S. Haddad, Ravi S. Sunkavalli, Wing Han Leung, John Chen, Ravi Prakash Gutala, Colin Bill, Vei-Han Chan
  • Patent number: 6122198
    Abstract: A method of erase verifying and overerase verifying an array of flash memory cells by erase verifying each memory cell bit-by-bit in a memory array, overerase verifying each memory cell bit-by-bit in the memory array after each memory cell verifies as erased and again erase verifying each memory cell bit-by-bit in the memory array after each cell overerase verifies. The threshold voltage of each memory cell is compared to the threshold voltage of a reference memory cell and an overerase correction pulse is applied to the column in which the overerased memory cell is located.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: September 19, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sameer Shafiq Haddad, Ravi Prakash Gutala, Colin Bill
  • Patent number: 5724284
    Abstract: A shift register page buffer for use in an array of multiple bits-per-cell flash EEPROM memory cells so as to render page mode programming and reading is provided. A sensing logic circuit (26,27) is used to selectively and sequentially compare array bit line voltages with each of a plurality of target reference cell bit line voltages. Shift register circuit (300) is responsive to the sensing logic circuit for sequentially storing either a low or high logic level after each comparison of the bit line voltages with one of the plurality of target reference voltages. Each of the shift register circuits is formed of series-connected latch circuits (302-308), each having inputs and outputs. A switching transistor (N5) is interconnected between the sensing logic circuit and the latch circuits and is responsive to a corresponding output of the latch circuits for selectively passing the logic signal from the sensing circuit means to the input of the latch circuits.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: March 3, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Colin Stewart Bill, Ravi Prakash Gutala, Qimeng Derek Zhou, Jonathan Shichang Su
  • Patent number: 5675537
    Abstract: An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 .mu.A from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: October 7, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Colin Stewart Bill, Jonathan Shichang Su, Ravi Prakash Gutala