Patents by Inventor Ravi Varadrajan

Ravi Varadrajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient apparatus and method for analysis of RTL structures that cause physical congestion
    Patent number: 8745567
    Abstract: A logical congestion metric analysis engine predicts pre-placement routing congestion of integrated circuit designs. The engine uses a method employing new congestion-predicting metrics derived from structural register transfer level (RTL). The method compares multiple metrics to those stored in a knowledge base to predict routing congestion. The knowledge base contains routing results for multiple designs using the same technology. For each design the knowledge base holds pre-placement metric values and the corresponding post-placement and routing congestion results. A logical congestion debug tool allows users to visualize and fix congestion issues.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: June 3, 2014
    Assignee: Atrenta, Inc.
    Inventors: Ravi Varadrajan, Jitendra Gupta, Priyank Mittal, Tapeesh Gupta, Navneet Mohindru