Patents by Inventor Ravinder K. Sharma

Ravinder K. Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5674780
    Abstract: A method of forming an electrically conductive polymer bump (22) over an aluminum electrode (21) produces low contact resistance for an interconnect structure (24). Aluminum oxide is first removed from the aluminum electrode (21). Tiron and palladium are subsequently bonded to the fresh surface of the aluminum electrode (21). Finally, the electrically conductive polymer bump (22) is formed over the aluminum electrode (21). The Tiron and palladium improve the electrical contact between the conductive polymer bump (22) and the aluminum electrode (21) thereby reducing the contact resistance. The Tiron also inhibits corrosion of the aluminum electrode (21) and enhances the conductivity by catalytically shrinking the cyanate ester conductive bump.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: October 7, 1997
    Assignee: Motorola, Inc.
    Inventors: William H. Lytle, Treliant Fang, Jong-Kai Lin, Ravinder K. Sharma, Naresh C. Saha
  • Patent number: 5555341
    Abstract: An electrically conductive waveguide is provided. A waveguide including a core region, a cladding region, a first surface and an end surface is fabricated. Cladding region covers a portion of the core region forming the first surface, and a portion of the core region and the cladding region form the end surface. The first surface and the end surface meet to form a nexus. An opening located at the nexus of the first surface and the end surface is formed with a conductive member located in the opening.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: September 10, 1996
    Assignee: Motorola, Inc.
    Inventors: Ravinder K. Sharma, Michael S. Lebby, Davis H. Hartman, Kent W. Hansen
  • Patent number: 5411400
    Abstract: A plurality of inserts (12) formed on a first substrate (11). A plurality of sockets (14) formed on a second substrate (13). Each socket of the plurality of sockets (14) on the second substrate (13) has a corresponding insert from the plurality of inserts (12) which physically aligns for coupling. At least one of the first (11) or second (13) substrates must be a semiconductor substrate. This arrangement allows for electrically connecting a semiconductor device or structure to another device for testing, burn-in, or final assembly.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: May 2, 1995
    Assignee: Motorola, Inc.
    Inventors: Ravichandran Subrahmanyan, Ravinder K. Sharma, William H. Lytle, Barry C. Johnson
  • Patent number: 4946376
    Abstract: A backside metalization scheme for semiconductor devices includes a vanadium layer disposed on the backside of a wafer and a silver layer disposed on the vanadium layer. An optional intermediate layer comprising either a mixture of vanadium and silver or nickel may be disposed between the vanadium layer and the silver layer. The vanadium layer exhibits excellent adhesion characteristics on the backside of wafers having a finish at least as fine as a 300 grit equivalency while the silver layer exhibits excellent solderability characteristics.
    Type: Grant
    Filed: April 6, 1989
    Date of Patent: August 7, 1990
    Assignee: Motorola, Inc.
    Inventors: Ravinder K. Sharma, William H. Lytle, Angela Rogona, Bennett L. Hileman
  • Patent number: 4927505
    Abstract: A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: May 22, 1990
    Assignee: Motorola Inc.
    Inventors: Ravinder K. Sharma, Harry J. Geyer, Douglas G. Mitchell
  • Patent number: 4880708
    Abstract: A titanium-tungsten-nitride/titanium-tungsten/gold (TiWN/TiW/Au) packaging interconnect metallization scheme is used to provide electrical contact to chip level interconnect metallization on a semiconductor substrate. The TiWN/TiW/Au packaging interconnect metallization scheme provides for good adhesion and barrier properties that withstand high temperatures and improve the reliability of the semiconductor chip. The TiWN layer provides good adhesion to the chip level interconnect metallization and the passivation layer. It also provides improved barrier properties to prevent the diffusion of other metal atoms through it. The TiW layer provides good adhesion to the gold metal layer. A gold bump may be electroplated to the gold layer and automatically bonded to a conductive lead of a tape in TAB packaging; or a wire bonded to the gold layer in conventional packaging.
    Type: Grant
    Filed: July 5, 1988
    Date of Patent: November 14, 1989
    Assignee: Motorola, Inc.
    Inventors: Ravinder K. Sharma, Harry J. Geyer, Douglas G. Mitchell