Abstract: A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be identified. The method also can include determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing information of the circuit design and generating a list specifying each empty site of the target device that has a routing conflict.

Abstract: A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

Abstract: Disclosed herein are methods, apparatus, and compositions for removing mercury gas from coal combustion emissions and the like. Disclosed herein is a gettering composition comprising an activated montmorillonite clay, a method for removing mercury from a gas stream using the gettering composition, and an apparatus for removing mercury from a gas stream.

Abstract: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

Abstract: A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Abstract: A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.

Abstract: A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.

Abstract: The invention provides a solution for transforming a flow graph model to a structured flow language model. In particular, the nodes in the flow graph model are traversed, and each node is mapped to an activity in the structured flow language model. When a node comprises a branch point, the corresponding branch region is identified and mapped. This process is repeated until all nodes in the flow graph model have been mapped to corresponding activities in the structured flow language model. In this manner, the desired nesting and containment relationships can be identified and generated in the structured flow language model.

Abstract: The invention provides a solution for generating a target process flow based on a source process flow of a different model format. In particular, for each element in the source process flow that maps to multiple elements in the target process flow, a container element is created in the target process flow to abstract the multiple elements, which are included in the container element. In this manner, visual consistency is maintained between the source process flow and target process flow, while also maintaining the semantics of the source process flow in the target process flow.

Abstract: A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.

Abstract: A method of implementing a user integrated circuit (IC) design in a tree representation includes the step of introducing the tree representation for the user IC design in a partitioned manner including at least one sub-design to form a design abstraction of the user design. At least one sub-design can include a sub-design providing for multiple levels of implementation hierarchy. The method can further include the step of traversing the design abstraction in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for at least one sub-design, and the step of traversing the design abstraction in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs. Traversing the design abstraction in the bottom-up fashion can facilitate a re-budgeting of timing for the integrated circuit design.

Abstract: Method, apparatus, and computer readable medium for determining signal routing cost within an integrated circuit is described. In an example, the integrated circuit is divided into topology units and includes routing resources. A respective span is determined in terms of one or more of the topology units for each of the routing resources. A cost value is assigned to each of the routing resources using the respective span associated therewith. A routing resource is selected from the routing resources. At least one distance between the routing resource and at least one other of the routing resources is calculated. A future cost value for the at least one distance is computed using the cost value assigned to the routing resource.

Abstract: A systematic method for calculating future cost is disclosed. Pre-routing is performed from a source node to other nodes through a series of neighboring nodes. At each node in the pre-routing, the cumulative routing cost and Manhattan distance are calculated. This cumulative routing cost is used as a new future cost for a specific distance if it is lower than or there is no existing future cost for that distance. A table can be used to store the future cost data. During routing, the recorded future cost is added to the cumulative cost of a node to help guide the routing, improving router run-time.

Abstract: A delay optimization algorithm has four major steps: (1) selecting signal connections to target for delay improvement; (2) unrouting all signals containing those candidate connections; (3) rerouting those signals, using a “load-balancing”heuristic; and (4) during rip-up and re-try routing, protecting wiring to all signal loads routed by the heuristic, including non-timing critical loads. Load balancing includes (a) applying a branching penalty on logic cell output wire segments, and (b) encouraging all non-route critical loads to route through a single buffered wire segment.

Abstract: A systematic method for calculating future cost is disclosed. Pre-routing is performed from a source node to other nodes through a series of neighboring nodes. At each node in the pre-routing, the cumulative routing cost and Manhattan distance are calculated. This cumulative routing cost is used as a new future cost for a specific distance if it is lower than or there is no existing future cost for that distance. A table can be used to store the future cost data. During routing, the recorded future cost is added to the cumulative cost of a node to help guide the routing, improving router run-time.

Abstract: The present invention provides a new method to handle a signal that crosses one or more areas in modular design of programmable logic devices. Even when the signal have an attribute disallowing the use of programmable interconnect points on an associated wire, the programmable interconnect points may still be used if the wire has no input programmable interconnect points outside of the attribute's associated area. This approach makes use of the programmable interconnect point directionalities and allows for more programmable interconnect points to be used while guaranteeing that the detailed routing solution is conflict free and absent of signal shorts.

Abstract: The present invention provides a new method to handle power and ground signals in modular design of programmable logic devices. During module implementation, the power and ground signals of each module are associated with area constraint properties. When performing routing in the module implementation phase, the power and ground signals together with regular local signals of the module are routed in accordance with their respective area constraint properties. However, the area constraint properties of the power and ground signals are removed during assembly phase while the area constraint properties of the local signals are retained.

Abstract: A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.

Abstract: The resource cost associated with each resource in a programmable logic device (PLD) can be obtained from topology information. In one embodiment, the PLD can be geometrically divided into an array of logical tiles. The cost can be set equal to the number of tiles the resource intersects (span). A signal path between a.source and a destination can be routed using this resource cost. In another embodiment, the cost is set as the maximum value between the vertical and horizontal spans (instead of the total span). This embodiment often increases the speed of routing.

Abstract: The present invention provides a new method to handle power and ground signals in modular design of programmable logic devices. During module implementation, the power and ground signals of each module are associated with area constraint properties. When performing routing in the module implementation phase, the power and ground signals together with regular local signals of the module are routed in accordance with their respective area constraint properties. However, the area constraint properties of the power and ground signals are removed during assembly phase while the area constraint properties of the local signals are retained.