Patents by Inventor Raymond Louis Barrett, Jr.

Raymond Louis Barrett, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170311668
    Abstract: A micro-electro-mechanical (MEMS) exhaust valve-based impact attenuating fluid filled cell for use in cushioning impact and decelerating of a wearer's body portion (e.g. head, shoulder, torso, etc.) after an impact. In combination with the use of accelerometers, pressure sensors, location and other electronics supply signals to a microcontroller, the controlled opening/closing of said exhaust valve (resulting in the expelling of said fluids with an optional combination with cell refill means) when certain parameters exceed a threshold.
    Type: Application
    Filed: July 12, 2017
    Publication date: November 2, 2017
    Inventor: Raymond Louis Barrett, JR.
  • Patent number: 9717298
    Abstract: A micro-electro-mechanical (MEMS) exhaust valve-based impact attenuating fluid filled cell for use in cushioning impact and decelerating of a wearer's body portion (e.g. head, shoulder, torso, etc.) after an impact. In combination with the use of accelerometers, pressure sensors, location and other electronics supply signals to a microcontroller, the controlled opening/closing of said exhaust valve (resulting in the expelling of said fluids with an optional combination with cell refill means) when certain parameters exceed a threshold.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: August 1, 2017
    Inventor: Raymond Louis Barrett, Jr.
  • Patent number: 9377805
    Abstract: Embodiments may include a method, system and apparatus for providing a reference voltage supply. A series resistor is provided between a power supply and a bandgap circuit coupled to an amplifier. A shunt transistor circuit is operatively coupled to the series resistor. A programmable output voltage is provided based upon the shunt transistor circuit and a first value of the series resistor.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 28, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raymond Louis Barrett, Jr., Mark Chirachanchai
  • Publication number: 20150102856
    Abstract: Embodiments may include a method, system and apparatus for providing a reference voltage supply. A series resistor is provided between a power supply and a bandgap circuit coupled to an amplifier. A shunt transistor circuit is operatively coupled to the series resistor. A programmable output voltage is provided based upon the shunt transistor circuit and a first value of the series resistor.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 16, 2015
    Inventors: Raymond Louis Barrett, JR., Mark Chirachanchai
  • Patent number: 6768398
    Abstract: A transmission line (218) is formed to have a characteristic impedance which increases at a first substantially exponential rate with respect to a distance from the input (202). A plurality of resonators (206-214) are coupled to the transmission line and positioned at a plurality of locations along the transmission line. The plurality of resonators has resonant frequencies that decrease at a second substantially exponential rate with respect to the distance from the input. An output signal (810, 812) is obtained at a point in the filter that produces a filter response having a corner frequency.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: July 27, 2004
    Assignee: Motorola, Inc.
    Inventors: Edgar Herbert Callaway, Jr., Raymond Louis Barrett, Jr., Gilberto Jacinto Hernandez, Douglas Harold Weisman
  • Patent number: 6573782
    Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: June 3, 2003
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry Herold, Scott Humphreys
  • Patent number: 6275540
    Abstract: A selective call receiver (500) includes a radio receiver (501) and a processor (508). The radio receiver includes an antenna (502), a combination circuit (204), a bandpass filter (208), mixers (212, 214), analog-to-digital converters (222, 224), digital mixers (234, 236), a second combination circuit (242), and a digital-to-analog converter (246). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: August 14, 2001
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., James G. Mittel, Barry W. Herold
  • Patent number: 6218973
    Abstract: A random number generator includes a sample clock having a sample clock rate, a chaotic oscillator having a characteristic upper frequency, and an output section. The chaotic oscillator includes a quantized linear section and a non-linear section. The quantized linear section includes multiple quantized integrators coupled to the sample clock and intercoupled in a linear intercoupling. The non-linear section is coupled in a feedback manner with the quantized linear section. The output section generates a random binary output signal having the sample clock rate, formed by a logical combination of binary signals, of which one binary signal is generated by each of the multiple quantized integrators. Each quantized integrator includes an analog to digital converter that preferably includes a sigma delta converter that generates one of the binary signals.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: April 17, 2001
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry W. Herold
  • Patent number: 6087894
    Abstract: A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: July 11, 2000
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry W. Herold, Scott Humphreys, Lawrence L. Case
  • Patent number: 5880619
    Abstract: A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: March 9, 1999
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry W. Herold, Grazyna A. Pajunen
  • Patent number: 5841822
    Abstract: A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: November 24, 1998
    Assignee: Motorola, Inc.
    Inventors: James Gregory Mittel, Raymond Louis Barrett, Jr., Walter Davis
  • Patent number: 5825213
    Abstract: A method and apparatus for frequency synthesis replaces a conventional divide-by-N counter with a low-power binary ripple counter (108). The method and apparatus employs a difference comparison scheme (114) that provides arbitrarily precise channel spacing, and allows loop sample rate to be selected independent of channel spacing.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: October 20, 1998
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry Herold, Grazyna A. Pajunen
  • Patent number: 5805095
    Abstract: A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: September 8, 1998
    Assignee: Motorola, Inc.
    Inventors: Scott Robert Humphreys, Raymond Louis Barrett, Jr., Lawrence Loren Case
  • Patent number: 5793825
    Abstract: A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: August 11, 1998
    Assignee: Motorola, Inc.
    Inventors: Scott Robert Humphreys, Raymond Louis Barrett, Jr., Barry W. Herold
  • Patent number: 5770980
    Abstract: A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.
    Type: Grant
    Filed: December 23, 1996
    Date of Patent: June 23, 1998
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., John Wayne Simmons, Barry Herold, Grazyna A. Pajunen
  • Patent number: 5768315
    Abstract: A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: June 16, 1998
    Assignee: Motorola, Inc.
    Inventors: James Gregory Mittel, Raymond Louis Barrett, Jr., Walter Davis
  • Patent number: 5754598
    Abstract: A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: May 19, 1998
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry W. Herold, Grazyna Anna Pajunen
  • Patent number: 5651037
    Abstract: A communication receiver (100) utilizing a synthesizer (143) employs a discrete-time phase locked loop which includes a reference oscillator (135), a phase error detector (202), a discrete-time analog computing element (206), an integrator (210), a controlled frequency generator (211, 212), and a frequency divider (214). The discrete-time analog computing element implements a discrete-time analog lead-lag network circuit. This circuit includes a clock and logic circuit (216), at least one discrete-time analog queuing element (218), and an analog computing engine (222). The queuing element (218) includes N analog signal lines, N analog storage lines, N control lines, and N.sup.2 controllable switches. Each controllable switch is coupled between each of the N analog signal lines and each of the N analog storage lines. In addition, N charge storage elements are coupled between each of the N analog storage lines and a common circuit node.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: July 22, 1997
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry W. Herold, Grazyna Anna Pajunen
  • Patent number: 5644743
    Abstract: A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: July 1, 1997
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry W. Herold, Grazyna Anna Pajunen, Walter L. Davis
  • Patent number: 5640681
    Abstract: A cascode current mirror circuit includes a cascode connected input stage (401) that operates to conduct an input current (400) in response to an input voltage of an input signal coupled to an effective transconductance of the cascode connected input stage (401). An input mirroring transistor (404) operates to control a mirror reference current (406) in response to the input voltage of the input signal. A diode connected transistor (409) coupled to a second control node of the cascode connected input stage (410) generates a control bias proportional to the mirror reference current (406) and to the input signal. A cascode connected output stage (411) has a first control node (413) coupled to the input signal and a second control node (414) coupled to the diode connected transistor (409) and the second control node (410) of the cascode connected input stage (401) for establishing an output current (415) that is substantially equivalent to the input current (400).
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: June 17, 1997
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry Wayne Herold, Grazyna A. Pajunen