Patents by Inventor Rebecca E. Hebda

Rebecca E. Hebda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7519799
    Abstract: Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single memory. A processor including multiple programmable logic arrays (PLAs); an instruction pointer queue coupled to the multiple PLAs; and an instruction pointer sequencing logic/predictor component coupled to the instruction pointer queue. The processor further includes a micro-operation cache coupled to the instruction pointer sequencing logic/predictor component; a micro-operation memory coupled to the micro-operation cache; and a trace pipe (TPIPE) coupled to the micro-operation cache and the instruction pointer queue.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Rebecca E. Hebda, Jourdan J. Stephan
  • Patent number: 7334115
    Abstract: The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Reynold V. D'Sa, Alan B. Kyker, Slade A. Morgan, Rebecca E. Hebda, Richard A. Weier, Robert F. Krick
  • Patent number: 6493821
    Abstract: A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: December 10, 2002
    Assignee: Intel Corporation
    Inventors: Reynold V. D'Sa, Robert F. Krick, Rebecca E. Hebda, Alan B. Kyker
  • Patent number: 6374350
    Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: April 16, 2002
    Assignee: Intel Corporation
    Inventors: Reynold V. D'Sa, Rebecca E. Hebda, Stavros Kalafatis, Alan B. Kyker, Robert B. Chaput
  • Patent number: 6151671
    Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: November 21, 2000
    Assignee: Intel Corporation
    Inventors: Reynold V. D'Sa, Rebecca E. Hebda, Stavros Kalafatis, Alan B. Kyker, Robert B. Chaput
  • Patent number: 6055630
    Abstract: An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: April 25, 2000
    Assignee: Intel Corporation
    Inventors: Reynold V. D'Sa, Alan B. Kyker, Gad S. Sheaffer, Gustavo P. Espinosa, Stavros Kalafatis, Rebecca E. Hebda