Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: A non-volatile storage device comprises non-volatile memory cells, clocked circuity, and one or more control circuits. The one or more control circuits are configured to process commands to access the non-volatile memory cells using the clocked circuity, implement a power control loop to regulate power consumption of the non-volatile storage device based on a first feedback signal, implement a temperature control loop to regulate temperature of the non-volatile storage device based on a second feedback signal, and implement a clock frequency control loop to regulate one or more clock frequencies of the clocked circuitry based on a third feedback signal.

Abstract: A non-volatile storage device comprises non-volatile memory cells, clocked circuity, and one or more control circuits. The one or more control circuits are configured to process commands to access the non-volatile memory cells using the clocked circuity, implement a power control loop to regulate power consumption of the non-volatile storage device based on a first feedback signal, implement a temperature control loop to regulate temperature of the non-volatile storage device based on a second feedback signal, and implement a clock frequency control loop to regulate one or more clock frequencies of the clocked circuitry based on a third feedback signal.

Abstract: To provide more uniform performance levels for solid state drive (SSDs), the static power level used by an SSD in an idle state is measured and used to determine a static power offset for each of the drives. The static power offset is set as a parameter for the SSD and used to offset a received power supply level for use on the drive. For a data storage system of multiple SSDs, a common scaling factor can be used to set the degree to which the static power offset is implemented, allowing for a choice between uniformity of power and uniformity of performance for the SSDs of a data storage system.

Abstract: A method for communicating digital display data and associated auxiliary processing data from a frame buffer to a post processor. The method includes storing the display data and the auxiliary processing data in the frame buffer, forming video scan lines from the frame buffer by handling both the display data and the auxiliary processing data as video data, and transferring the video scan lines over a digital video interface to a post-processor.

Abstract: A method and apparatus for accessing a cache memory of a computer graphics system, the apparatus including a frame buffer memory having a graphics memory for storing pixel data for ultimate supply to a video display device, a read cache memory for storing data received from the graphics memory, and a write cache memory for storing data received externally of the frame buffer and data that is to be written into the graphics memory. Also included is a frame buffer controller for controlling access to the graphics memory and read and write cache memories. The frame buffer controller includes a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memories.

Abstract: A self contained portable sprayer system including a tank for receiving a fluid mixture and has a top portion with a cap coupled by a threadable connection. The tank has a flat bottom portion. A fluid release valve with a fluid release tube threadably connected to the top portion of the tank. The release valve has a pair of flexible hoses. A pressure switch that has an air receiving tube at one end threadably connected to the top portion. The pressure switch has a pressure hose. A pressure release valve is positioned on the top portion of the tank. A towing hitch for carrying the tank has, an elongated vertical portion, a short vertical portion, and a flat lower portion. The elongated portion has a distal side with a pair of wheels, and one shelf supporting a power source. The lower portion seats the tank when positioned within the towing hitch. Lastly, a cyclic air pump is positioned on another shelf of the elongated portion and forces air into the tank.