Abstract: Embodiments disclosed herein include a method of monitoring a photoresist deposition process. In an embodiment, the method comprises depositing a photoresist layer to a first thickness over a substrate, measuring a property of the photoresist layer with a first electromagnetic (EM) radiation source, depositing the photoresist layer to a second thickness over the substrate, and measuring the property of the photoresist layer with the first EM radiation source.

Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.

Abstract: Embodiments disclosed herein include methods of developing a metal oxo photoresist. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a vacuum chamber, where the metal oxo photoresist comprises exposed regions and unexposed regions. In an embodiment, the unexposed regions comprise a higher carbon concentration than the exposed regions. The method may further comprise vaporizing a halogenating agent into the vacuum chamber, where the halogenating agent reacts with either the unexposed regions or the exposed regions to produce a volatile byproduct. In an embodiment, the method may further comprise purging the vacuum chamber.

Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.

Abstract: Embodiments disclosed herein include methods of developing a metal oxo photoresist. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a vacuum chamber, where the metal oxo photoresist comprises exposed regions and unexposed regions. In an embodiment, the unexposed regions comprise a higher carbon concentration than the exposed regions. The method may further comprise vaporizing a halogenating agent into the vacuum chamber, where the halogenating agent reacts with either the unexposed regions or the exposed regions to produce a volatile byproduct. In an embodiment, the method may further comprise purging the vacuum chamber.

Abstract: Embodiments disclosed herein include methods of developing a metal oxo photoresist. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a vacuum chamber, where the metal oxo photoresist comprises exposed regions and unexposed regions. In an embodiment, the unexposed regions comprise a higher carbon concentration than the exposed regions. The method may further comprise vaporizing a halogenating agent into the vacuum chamber, where the halogenating agent reacts with either the unexposed regions or the exposed regions to produce a volatile byproduct. In an embodiment, the method may further comprise purging the vacuum chamber.

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.

Abstract: Embodiments include a method of forming a metal oxo photoresist on a substrate. In an embodiment, the method comprises providing a target in a vacuum chamber, where the target comprises a metal. The method may continue with flowing a hydrocarbon gas and an inert gas into the vacuum chamber, and striking a plasma in the vacuum chamber. In an embodiment, the method further continues with depositing the metal oxo photoresist on the substrate, where the metal oxo photoresist comprise metal-carbon bonds and metal-oxygen bonds.

Abstract: Processing methods to etch metal oxide films with less etch residue are described. The methods comprise etching a metal oxide film with a metal halide etchant, and exposing the etch residue to a reductant to remove the etch residue. Some embodiments relate to etching tungsten oxide films. Some embodiments utilize tungsten halides to etch metal oxide films. Some embodiments utilize hydrogen gas as a reductant to remove etch residues.

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.

Abstract: Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method for forming a photoresist layer over a substrate in a vacuum chamber comprises providing a metal precursor vapor into the vacuum chamber. In an embodiment, the method further comprises providing an oxidant vapor into the vacuum chamber, where a reaction between the metal precursor vapor and the oxidant vapor results in the formation of the photoresist layer on a surface of the substrate. In an embodiment, the photoresist layer is a metal oxo containing material.

Abstract: Embodiments disclosed herein include methods of developing a metal oxo photoresist. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a vacuum chamber, where the metal oxo photoresist comprises exposed regions and unexposed regions. In an embodiment, the unexposed regions comprise a higher carbon concentration than the exposed regions. The method may further comprise vaporizing a halogenating agent into the vacuum chamber, where the halogenating agent reacts with either the unexposed regions or the exposed regions to produce a volatile byproduct. In an embodiment, the method may further comprise purging the vacuum chamber.

Abstract: Embodiments disclosed herein include a method of developing a metal oxo photoresist with a non-wet process. In an embodiment, the method comprises providing a substrate with the metal oxo photoresist into a chamber. In an embodiment, the metal oxo photoresist comprises exposed regions and unexposed regions, and the unexposed regions comprise a higher carbon concentration than the exposed regions. In an embodiment, the method further comprises flowing a gas into the chamber, wherein the gas reacts with the unexposed regions to produce a volatile byproduct.

Abstract: Disclosed are methods for reducing transfer pattern defects in a semiconductor device. In some embodiments, a method includes providing a semiconductor device including a plurality of photoresist lines on a stack of layers, wherein the plurality of photoresist lines includes a bridge defect extending between two or more photoresist lines of the plurality of photoresist lines. The method may further include forming a plurality of mask lines by etching a set of trenches in a first layer of the stack of layers, and removing the bridge defect by etching the bridge defect at a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the stack of layers.

Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.

Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.