Patents by Inventor Regis Crinon
Regis Crinon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7957307Abstract: An error correction system determines a level of error correction protection to apply to a frame of video data to be transmitted by a sending endpoint to a receiving endpoint based on the predicted impact of packet loss as well as the importance of the frame based on inter-frame dependencies, frame size, packet loss probability, historical packet loss pattern, central processing unit (CPU) load, and available network bandwidth. At the receiving endpoint, when packet loss is detected for a particular frame, the receiving endpoint will attempt to recover the frame using protection packets received along with the video data.Type: GrantFiled: March 14, 2007Date of Patent: June 7, 2011Assignee: Microsoft CorporationInventors: Jingyu Qiu, Timothy M. Moore, Guo-Wei Shieh, Zong Zong Yuan, Regis Crinon, Arvind Jayasundar
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Publication number: 20080225735Abstract: An error correction system determines a level of error correction protection to apply to a frame of video data to be transmitted by a sending endpoint to a receiving endpoint based on the predicted impact of packet loss as well as the importance of the frame based on inter-frame dependencies, frame size, packet loss probability, historical packet loss pattern, central processing unit (CPU) load, and available network bandwidth. At the receiving endpoint, when packet loss is detected for a particular frame, the receiving endpoint will attempt to recover the frame using protection packets received along with the video data.Type: ApplicationFiled: March 14, 2007Publication date: September 18, 2008Applicant: Microsoft CorporationInventors: Jingyu Qiu, Timothy M. Moore, Guo-Wei Shieh, Zong Zong Yuan, Regis Crinon, Arvind Jayasundar
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Publication number: 20070130493Abstract: Feedback and frame synchronization between media encoders and decoders is described. More particularly, the encoder can encode frames that are based on source content to be sent to the decoder. The encoder can determine whether the frame should be cached by the encoder and the decoder. If the frame is to be cached, the encoder can so indicate by encoding the frame with one or more cache control bits. The decoder can receive the frame from the decoder, and can examine the cache control bits to determine whether to cache the frame. The decoder can also decode the frame.Type: ApplicationFiled: December 7, 2005Publication date: June 7, 2007Applicant: Microsoft CorporationInventors: Warren Barkley, Regis Crinon, Chih-Lung Lin, Tim Moore, Wei Zhong, Minghui Xia
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Publication number: 20060104356Abstract: Techniques and tools are described for using various bitstream elements to determine a time interval between successive examinations of a decoder buffer while decoding a video bitstream. For example, a first bitstream element in a first syntax layer above frame layer in a video bitstream is processed. That element indicates whether a repeat-picture element is present in frame data that is also processed. The first bitstream element and, if present, the repeat-picture element are used to determine a time interval between two successive examinations of a decoder buffer while decoding the bitstream, such that the time interval is indicated by a target display duration for a video access unit, such as a frame or a field of the bitstream.Type: ApplicationFiled: November 15, 2004Publication date: May 18, 2006Applicant: Microsoft CorporationInventor: Regis Crinon
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Publication number: 20060087586Abstract: A closed captioning configuration system is described. The system receives parameters of a digital video presentation and computes closed captioning parameters to drive a closed captions encoder, creating closed captions which are compatible with the presentation. In various implementations, the configuration system may be integrated into a video encoder, a closed captions encoder, or both. The configuration system, through analysis of the presentation parameters, can drive captioning for presentations which may differ by frame rate, interlacing, or frame encoding mode, and account for repetition of fields or frames.Type: ApplicationFiled: October 25, 2004Publication date: April 27, 2006Inventor: Regis Crinon
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Publication number: 20060036759Abstract: The techniques and mechanisms described herein are directed at transmitting elementary streams in a broadcast environment. The mechanisms provide a buffer controller and packet scheduler that allow a media format to be transmitted through the broadcasting environment in a manner resulting in a low channel switch delay. A buffer-fullness indicator allows the operation with various types of decoders. A lower bound and an upper bound are calculated for each frame within the elementary stream. The lower bound corresponds to an earliest time for sending the frame without causing an overflow condition within a decoder buffer. The upper bound corresponds to a latest time for sending the frame without causing an underflow condition within the decoder buffer. A send time is then scheduled based on the lower bound and the upper bound that determines when a packet associated with the frame is transmitted over a channel in a broadcast environment.Type: ApplicationFiled: August 12, 2004Publication date: February 16, 2006Applicant: Microsoft CorporationInventors: Guobin Shen, Shipeng Li, Hua Cai, Regis Crinon, Ze-wen Zhang, Guangping Gao, Hong-Hui Sun, Baogang Yao
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Publication number: 20050152448Abstract: A video decoder receives an entry point key frame comprising first and second interlaced video fields and decodes a first syntax element comprising information (e.g., frame coding mode) for the entry point key frame at a first syntax level (e.g., frame level) in a bitstream. The first interlaced video field is a predicted field, and the second interlaced video field is an intra-coded field. The information for the entry point key frame can be a frame coding mode (e.g., field interlace) for the entry point key frame. The decoder can decode a second syntax element at the first syntax level comprising second information (e.g., field type for each of the first and second interlaced video fields) for the entry point key frame.Type: ApplicationFiled: November 15, 2004Publication date: July 14, 2005Applicant: Microsoft CorporationInventors: Regis Crinon, Thomas Holcomb, Shankar Regunathan, Sridhar Srinivasan
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Publication number: 20050135783Abstract: A video receiver system comprises a video elementary stream decoder that decodes an elementary stream and one or more trick mode processing modules that modify the elementary stream to enable a trick mode effect. The trick mode processing module(s) produce a trick mode elementary stream for input to the video elementary stream decoder module. For example, the one or more trick mode processing modules can replace plural non-key frames of the elementary stream with one or more P-type skipped frames for a fast forward effect, where the trick mode elementary stream comprises one or more entry point key frames and the one or more P-type skipped frames. The video receiver system can selectively route the elementary stream to either the video elementary stream decoder module or the one or more trick mode processing modules.Type: ApplicationFiled: November 15, 2004Publication date: June 23, 2005Applicant: Microsoft CorporationInventor: Regis Crinon
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Publication number: 20050123274Abstract: A decoder receives an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header. The entry point header is in an entry point layer of a bitstream comprising plural layers. The decoder decodes the entry point header. The plural control parameters can include various combinations of control parameters such as a pan scan on/off parameter, a reference frame distance on/off parameter, a loop filtering on/off parameter, a fast chroma motion compensation on/off parameter, an extended range motion vector on/off parameter, a variable sized transform on/off parameter, an overlapped transform on/off parameter, a quantization decision parameter, and an extended differential motion vector coding on/off parameter, a broken link parameter, a closed entry parameter, one or more coded picture size parameters, one or more range mapping parameters, a hypothetical reference decoder buffer parameter, and/or other parameter(s).Type: ApplicationFiled: November 15, 2004Publication date: June 9, 2005Applicant: Microsoft CorporationInventors: Regis Crinon, Chih-Lung Lin, Jie Liang, Shankar Regunathan, Shuo-Jen Wu, Timothy Onders, Thomas Holcomb
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Publication number: 20050108772Abstract: An implementation is described herein that generally pertains to digital video television technology. At least one implementation, described herein, provides an asset definition framework for digital television (DTV) managed applications. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.Type: ApplicationFiled: November 19, 2003Publication date: May 19, 2005Inventors: Regis Crinon, Akash Pai
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Publication number: 20050105883Abstract: Techniques and tools for coding/decoding of digital video, and in particular, for determining, signaling and detecting entry points in video streams are described. Techniques and tools described herein are used to embed entry point indicator information in the bitstream that receivers, editing systems, insertion systems, and other systems can use to detect valid entry points in compressed video.Type: ApplicationFiled: June 30, 2004Publication date: May 19, 2005Applicant: Microsoft CorporationInventors: Thomas Holcomb, Regis Crinon, Timothy Onders, Sridhar Srinivasan, Shankar Regunathan
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Publication number: 20050099869Abstract: A decoder receives a field start code for an entry point key frame. The field start code indicates a second coded interlaced video field in the entry point key frame following a first coded interlaced video field in the entry point key frame and indicates a point to begin decoding of the second coded interlaced video field. The first coded interlaced video field is a predicted field, and the second coded interlaced video field is an intra-coded field. The decoder decodes the second field without decoding the first field. The field start code can be followed by a field header. The decoder can receive a frame header for the entry point key frame. The frame header may comprise a syntax element indicating a frame coding mode for the entry point key frame and/or a syntax element indicating field types for the first and second coded interlaced video fields.Type: ApplicationFiled: November 15, 2004Publication date: May 12, 2005Applicant: Microsoft CorporationInventors: Regis Crinon, Thomas Holcomb, Shankar Regunathan, Sridhar Srinivasan
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Publication number: 20050074061Abstract: Techniques and tools are described for signaling hypothetical reference decoder parameters for video bitstreams, including signaling of buffer fullness. For example, a buffer size syntax element indicates a decoder buffer size, and a buffer fullness syntax element indicates a buffer fullness as a fraction of the decoder buffer size. As another example, buffer fullness is signaled in one or more entry point headers and other hypothetical reference decoder parameters are signaled in a sequence header.Type: ApplicationFiled: September 2, 2004Publication date: April 7, 2005Applicant: Microsoft CorporationInventors: Jordi Ribas-Corbera, Sridhar Srinivasan, Shankar Regunathan, Regis Crinon
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Publication number: 20050069039Abstract: Techniques and tools are described for using a signaled or derived buffer fullness value to determine a decoding time stamp. The decoding time stamp can be used in a layer such as a system layer to determine when an access unit such as a coded representation of a field or frame should be decoded. For example, a decoding time stamp that corresponds to a clock cycle of a decoder is determined based at least in part on a hypothetical reference decoder initial buffer fullness value. An initial data access unit of a bitstream is transferred to the decoder for decoding at about the time of the corresponding clock cycle for the decoding time stamp.Type: ApplicationFiled: November 15, 2004Publication date: March 31, 2005Applicant: Microsoft CorporationInventor: Regis Crinon