Patents by Inventor Reinhold Wahlich
Reinhold Wahlich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070267142Abstract: Treatment of a semiconductor wafer employs: a) position-dependent measuring of a parameter characterizing the semiconductor wafer to determine a position-dependent value of the parameter over an entire surface of the semiconductor wafer, b) oxidizing the entire surface of the semiconductor wafer under the action of an oxidizing agent with simultaneous exposure of the entire surface, the oxidation rate and thus the thickness of the resulting oxide layer dependent on the light intensity at the surface of the semiconductor wafer, and c) removing of the oxide layer, the light intensity in step b) predefined in a position-dependent manner such that differences in the position-dependent values of the parameter measured are reduced by the position-dependent oxidation rate resulting in step b) and subsequent removal of the oxide layer in step c).Type: ApplicationFiled: May 17, 2007Publication date: November 22, 2007Applicant: SILTRONIC AGInventors: Brian Murphy, Diego Feijoo, Reinhold Wahlich
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Patent number: 7279700Abstract: A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of periodically arranged cavities below the surface. The invention also relates to a process for producing this semiconductor substrate and to an sSOI wafer produced from this semiconductor substrate.Type: GrantFiled: November 3, 2005Date of Patent: October 9, 2007Assignee: Siltronic AGInventors: Dirk Dantz, Andreas Huber, Reinhold Wahlich, Brian Murphy
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Patent number: 7235863Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ O ? ? i ] < [ O ? ? i ] eq ? ( T ) ? exp ? ? 2 ? ? SiO ? 2 ? ? r ? ? k ? ? T is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit solubility of oxygen in silicon at a temperature T, ?SiO2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP radius and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least paType: GrantFiled: July 16, 2004Date of Patent: June 26, 2007Assignee: Siltronic AGInventors: Christoph Seuring, Robert Hölzl, Reinhold Wahlich, Wilfried Von Ammon
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Publication number: 20060278157Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon water by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ Oi ] < [ Oi ] eq ? ( T ) ? exp ? 2 ? ? SiO ? ? ? 2 ? ? rkT is satisfied where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit colubility of oxygen in silicon at a temperature T, ?sio2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least part of the time being exposed to an oxygen-containingType: ApplicationFiled: June 29, 2006Publication date: December 14, 2006Applicant: Siltronic AGInventors: Christoph Seuring, Robert Hoelzl, Reinhold Wahlich, Wilfried Von Ammon
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Patent number: 7122865Abstract: An SOI wafer, includes a substrate made from silicon, an electrically insulating layer with a thermal conductivity of at least 1.6 W/(Km) and a single-crystal silicon layer with a thickness of from 10 nm to 10 ?m, a standard deviation of at most 5% from the mean layer thickness and a density of at most 0.5 HF defects/cm2. A process is for producing an SOI wafer of this type, in which a substrate wafer made from silicon is joined to a donor wafer via a layer of the electrically insulating material which has previously been applied. The donor wafer bears a donor layer of single-crystal silicon, with a concentration of vacancies of at most 1012/cm3 and of vacancy agglomerates of at most 105/cm3. After the wafers have been joined, the thickness of the donor wafer is reduced in such a manner that the single-crystal silicon layer having these properties is formed from the donor layer, this single-crystal silicon layer being joined to the substrate wafer via the layer of electrically insulating material.Type: GrantFiled: May 25, 2004Date of Patent: October 17, 2006Assignee: Siltronic AGInventors: Robert Hölzl, Dirk Dantz, Andreas Huber, Ulrich Lambert, Reinhold Wahlich
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Publication number: 20060213424Abstract: A silicon wafer having no epitaxially deposited layer or layer produced by joining to the silicon wafer, with a nitrogen concentration of 1·1013-8·1014 atoms/cm3, an oxygen concentration of 5.2·1017-7.5·1017 atoms/cm3, a central thickness BMD density of 3·108-2·1010 cm?3, a cumulative length of linear slippages ?3 cm and a cumulative area of areal slippage regions ?7 cm2, the front surface having <45 nitrogen-induced defects of >0.13 ?m LSE in the DNN channel, a layer at least 5 ?m thick, in which ?1·104 COPs/cm3 with a size of ?0.09 ?m occur, and a BMD-free layer ?5 ?m thick. Such wafers may be produced by heat treating the silicon wafer, resting on a substrate holder, a specific substrate holder used depending on the wafer doping. For each holder, maximum heating rates are selected to avoid formation of slippages.Type: ApplicationFiled: March 22, 2006Publication date: September 28, 2006Inventors: Timo Mueller, Wilfried von Ammon, Erich Daub, Peter Krottenthaler, Klaus Messmann, Friedrich Passek, Reinhold Wahlich, Arnold Kuehhorn, Johannes Studener
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Publication number: 20060202310Abstract: SOI wafers are manufactured to have very thin device layers of high surface quality. The layer is ? 20 nm in thickness, has an HF density of ? 0.1/cm2, and a surface roughness of 0.2 nm RMS.Type: ApplicationFiled: March 20, 2006Publication date: September 14, 2006Applicant: Siltronic AGInventors: Brian Murphy, Reinhold Wahlich, Rudiger Schmolke, Wilfried Von Ammon, James Moreland
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Publication number: 20060145188Abstract: A semiconductor wafer has a monocrystalline silicon layer and a graded silicon-germanium layer adjacent thereto, of thickness d and composition Si1-xGex, where x represents the proportion of germanium and 0<x?1, and where x assumes greater values with increasing distance a from the monocrystalline silicon layer, wherein the relationship between the proportion x(d) of germanium at the surface of the graded silicon-germanium layer and the proportion x(d/2) of germanium at the center distance between the monocrystalline silicon layer and the surface of the graded silicon-germanium layer is x(d/2)>0.5·x(d). The wafer may be further processed, in which process a layer of the semiconductor wafer is transferred to a substrate wafer.Type: ApplicationFiled: January 3, 2006Publication date: July 6, 2006Applicant: Siltronic AGInventors: Dirk Dantz, Andreas Huber, Reinhold Wahlich
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Publication number: 20060138540Abstract: The invention relates to a semiconductor wafer, which, at its surface comprises a semiconductor surface layer with a thickness in the range from 3 nm to 200 nm having no hole defects, and which comprises an adjoining electrically insulating layer beneath the semiconductor surface layer.Type: ApplicationFiled: December 21, 2005Publication date: June 29, 2006Applicant: Siltronic AGInventors: Dirk Dantz, Andreas Huber, Brian Murphy, Reinhold Wahlich
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Patent number: 7052948Abstract: The invention relates to a film or a layer made of semi-conducting material with low defect density in the thin layer, and a SOI-disk with a thin silicon layer exhibiting low surface roughness, defect density and thickness variations. The invention also relates to a method for producing a film or a layer made of semi-conductive material. Said method comprises the following steps: a) producing structures from a semi-conductive material with periodically repeated recesses which have a given geometrical structure, b) thermally treating the surface structured material until a layer with periodically repeated hollow spaces is formed under a closed layer on the surface of the material, c) separating the closed layer on the surface along the layer of hollow spaces from the remainder of the semi-conductive material.Type: GrantFiled: June 27, 2002Date of Patent: May 30, 2006Assignee: Siltronic AGInventors: Brian Murphy, Reinhold Wahlich, Rüdiger Schmolke, Wilfried Von Ammon, James Moreland
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Publication number: 20060097317Abstract: A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100% by weight, and a layer of periodically arranged cavities below the surface. The invention also relates to a process for producing this semiconductor substrate and to an sSOI wafer produced from this semiconductor substrate.Type: ApplicationFiled: November 3, 2005Publication date: May 11, 2006Applicant: Siltronic AGInventors: Dirk Dantz, Andreas Huber, Reinhold Wahlich, Brian Murphy
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Publication number: 20060097355Abstract: Semiconductor wafers are leveled by a) position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, b) etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate, semiconductor wafers with improved flatness and nanotopography and SOI wafer with improved layer thickness homogeneity are achieved. An apparatus for carrying out the method is also disclosed.Type: ApplicationFiled: November 7, 2005Publication date: May 11, 2006Applicant: Siltronic AGInventors: Theresia Bauer, Robert Hoelzl, Andreas Huber, Reinhold Wahlich
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Publication number: 20060046431Abstract: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 ?m, a DeltaWarp of less than 30 ?m, a bow of less than 10 ?m and a DeltaBow of less than 10 ?m. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.Type: ApplicationFiled: August 18, 2005Publication date: March 2, 2006Applicant: Siltronic AGInventors: Markus Blietz, Robert Hoelzl, Reinhold Wahlich, Andreas Huber
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Publication number: 20050287767Abstract: A process for producing a semiconductor substrate comprising a carrier wafer and a layer of single-crystalline semiconductor material: a) producing a layer containing recesses at the surface of a donor wafer of single-crystalline semiconductor material, b) joining the surface of the donor wafer containing recesses to the carrier wafer, c) heat treating to close the recesses at the interface between the carrier wafer and the donor wafer to form a layer of cavities within the donor wafer, and d) splitting the donor wafer along the layer of cavities, resulting in a layer of semiconductor material on the carrier wafer. Semiconductor substrates prepared thusly may have a single-crystalline semiconductor layer having a thickness of 100 nm or less, a layer thickness uniformity of 5% or less, and an HF defect density of 0.02/cm2 or less.Type: ApplicationFiled: June 21, 2005Publication date: December 29, 2005Inventors: Dirk Dantz, Andreas Huber, Reinhold Wahlich, Brian Murphy
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Publication number: 20050245048Abstract: An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/G<(v/G)crit=1.3×10?3 cm2/(K·min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.Type: ApplicationFiled: April 13, 2005Publication date: November 3, 2005Applicant: Siltronic AGInventors: Dieter Graf, Markus Blietz, Reinhold Wahlich, Alfred Miller, Dirk Zemke
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Publication number: 20050032376Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ O ? ? ? i ] < [ O ? ? ? i ] eq ? ( T ) ? exp ? ? ? 2 ? ? SiO ? 2 ? ? r ? ? ? k ? ? ? T is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit solubility of oxygen in silicon at a temperature T, ?SiO2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP radius and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least partType: ApplicationFiled: July 16, 2004Publication date: February 10, 2005Inventors: Christoph Seuring, Robert Holzl, Reinhold Wahlich, Wilfried Ammon
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Publication number: 20040251500Abstract: An SOI wafer, includes a substrate made from silicon, an electrically insulating layer with a thermal conductivity of at least 1.6 W/(Km) and a single-crystal silicon layer with a thickness of from 10 nm to 10 &mgr;m, a standard deviation of at most 5% from the mean layer thickness and a density of at most 0.5 HF defects/cm2.Type: ApplicationFiled: May 25, 2004Publication date: December 16, 2004Applicant: SILTRONIC AGInventors: Robert Holzl, Dirk Dantz, Andreas Huber, Ulrich Lambert, Reinhold Wahlich
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Patent number: 6803331Abstract: A process for the heat treatment of a silicon wafer, during which the silicon wafer is at least temporarily exposed to an oxygen-containing atmosphere, the heat treatment taking place at a temperature which is selected in such a way that the inequality [ Oi ] < [ Oi ] eq ⁢ ( T ) ⁢ exp ⁢ ( 2 ⁢ σ SiO 2 ⁢ Ω rkT ) is satisfied, where [Oi] is the oxygen concentration in the silicon wafer [Oi]eq(T) is the limit solubility of oxygen in silicon at a temperature T, &sgr;SiO2 is the surface energy of silicon dioxide &OHgr; is the volumType: GrantFiled: February 4, 2003Date of Patent: October 12, 2004Assignee: Siltronic AGInventors: Robert Hölzl, Christoph Seuring, Reinhold Wahlich, Wilfried Von Ammon
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Publication number: 20040142542Abstract: The invention relates to a film or a layer made of semiconducting material with low defect density in the thin layer, and a SOI-disk with a thin silicon layer exhibiting low surface roughness, defect density and thickness variations. The invention also relates to a method for producing a film or a layer made of semi-conductive material. Said method comprises the following steps: a) producing structures from a semi-conductive material with periodically repeated recesses which have a given geometrical structure, b) thermally treating the surface structured material until a layer with periodically repeated hollow spaces is formed under a closed layer on the surface of the material, c) separating the closed layer on the surface along the layer of hollow spaces from the remainder of the semi-conductive material.Type: ApplicationFiled: December 18, 2003Publication date: July 22, 2004Inventors: Brian Murphy, Reinhold Wahlich, Rudiger Schmolke, Wilfried Von Ammon, James Moreland
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Publication number: 20030148634Abstract: A process for the heat treatment of a silicon wafer, during which the silicon wafer is at least temporarily exposed to an oxygen-containing atmosphere, the heat treatment taking place at a temperature which is selected in such a way that the inequality 1 [ Oi ] < [ Oi ] eq ⁢ ( T ) ⁢ exp ⁢ ( 2 ⁢ σ SiO 2 ⁢ Ω rkT )Type: ApplicationFiled: February 4, 2003Publication date: August 7, 2003Applicant: Wacker Siltronic AG.Inventors: Robert Holzl, Christoph Seuring, Reinhold Wahlich, Wilfried Von Ammon