Patents by Inventor Remi COQUAND

Remi COQUAND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515392
    Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: November 29, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay Reboh, Remi Coquand, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang
  • Patent number: 11450755
    Abstract: An electronic device is provided, including a transistor and a substrate surmounted by first through third elements, the second element being arranged between the first and the third elements and including a nano-object, a transistor channel area being formed by part of the nano-object, a first end of the nano-object being connected to the first element by a first electrode including a first part forming a first continuity of matter and a second part formed on the first part, a second end of the nano-object being connected to the third element by a second electrode including a first part forming a second continuity of matter and a second part formed on the first part, such that a lattice parameter of the second part is suited to a lattice parameter of the first part to induce a stress in the nano-object along a reference axis.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: September 20, 2022
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 11177371
    Abstract: A method is provided for fabricating a double gate structure for transistors with superposed bars, including: providing, on a support, a stack including an alternation of one or several first bars based on a first semiconducting material, and one or several second bars based on a second semiconducting material; removing lateral portions of the second bars; forming insulating plugs in contact with lateral regions of the second bars; removing the first bars; and forming a gate electrode facing an upper face and a lower face of the second bars, the insulating plugs being arranged in contact with the lateral regions of the second bars when the gate electrode is being formed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: November 16, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Shay Reboh
  • Publication number: 20210328014
    Abstract: An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay REBOH, Remi COQUAND, Nicolas LOUBET, Tenko YAMASHITA, Jingyun ZHANG
  • Publication number: 20210257450
    Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 19, 2021
    Inventors: Nicolas Loubet, Tenko Yamashita, Guillaume Audoit, Nicolas Bernier, Remi Coquand, Shay Reboh
  • Patent number: 11088247
    Abstract: A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 10, 2021
    Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, International Business Machines Corporation
    Inventors: Shay Reboh, Kangguo Cheng, Remi Coquand, Nicolas Loubet
  • Patent number: 11081547
    Abstract: A method for making first and second superimposed transistors, including: making, on a substrate, a stack of several semiconducting nanowires; etching a first nanowire so that a remaining portion of the first nanowire forms a channel of the first transistor; etching a second nanowire arranged between the substrate and the first nanowire, so that a remaining portion of the second nanowire forms a channel of the second transistor and has a greater length than that of the remaining portion of the first nanowire; making second source and drain regions in contact with ends of the remaining portion of the second nanowire; depositing a first dielectric encapsulation layer covering the second source and drain regions and forming vertical insulating portions; making first source and drain regions in contact with ends of the remaining portion of the first nanowire and insulated from the second source and drain regions by the vertical insulating portions.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 3, 2021
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay Reboh, Remi Coquand, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang
  • Patent number: 11049933
    Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 29, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Loubet, Tenko Yamashita, Guillaume Audoit, Nicolas Bernier, Remi Coquand, Shay Reboh
  • Publication number: 20210020743
    Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Inventors: Nicolas Loubet, Tenko Yamashita, Guillaume Audoit, Nicolas Bernier, Remi Coquand, Shay Reboh
  • Patent number: 10896956
    Abstract: FET transistor (100) comprising: a semiconductor portion (104) of which a first part (106) forms a channel; a gate (108) at least partly surrounding the first part; internal dielectric spacers (112) arranged around doped second parts (114) of the semiconductor portion between which the first part is arranged and which form extension regions; electrically conductive portions (120) in contact with doped surfaces of extremities (118) of the semiconductor portion and with doped surfaces of third parts (116) of the semiconductor portion, forming part of the source and drain regions, at least partly surrounding the third parts, with each of the second parts being arranged between the first part and one of the third parts.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: January 19, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Remi Coquand, Shay Reboh
  • Patent number: 10818775
    Abstract: The method for fabricating a field-effect transistor comprises a step of producing a sacrificial gate and first and second spacers covering first, second and third parts of successive first to fifth semiconductor nanowires of a stack. The fabricating method comprises a step of forming a channel area of the transistor, which channel area is compressively stressed and distinct from the second part of the third nanowire. The channel area is connected to a source electrode of the transistor by the first part of the second nanowire, and to a drain electrode of the transistor by the third part of the second nanowire.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 27, 2020
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, International Business Machines Corporation
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20200321452
    Abstract: An electronic device is provided, including a transistor, a substrate surmounted by first, second, and third elements, the second arranged between the first and the third and including a nano-object, a channel area of the transistor formed by part of the nano-object, the nano-object including first and second opposite ends along a reference axis passing through the ends, the first end connected to the first element via a first electrode including a first part and a second part formed on the first part, the second end connected to the third element via a second electrode including a first part and a second part formed on the first part, the first parts formed of a first material and the second parts formed of a second material, a lattice parameter of the second material suited to that of the first material to induce a stress in the nano-object along the reference axis.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND, Nicolas LOUBET
  • Patent number: 10727320
    Abstract: A method of manufacturing a field effect transistor is provided, including supplying a substrate surmounted by first, second, and third structures, the second structure arranged between the first and the third structures and including at least one first nano-object located away from the substrate, a part of the first nano-object being configured to form a channel area of the transistor; forming electrodes of the transistor including epitaxial growth of a first material to obtain a first continuity of matter made of the first material between the second structure and the first structure, and to obtain a second continuity of matter made of the first material between the second structure and the third structure; and epitaxial growth of a second material, starting from the first material, the second material having a lattice parameter different from a lattice parameter of the first material of the first and the second continuities.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Patent number: 10714392
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Publication number: 20200212179
    Abstract: A method of fabrication of a semiconductor device including implementation of fabrication of at least one stack made on a substrate, including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, so the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure, and wherein the first or second semiconductor is capable of being selectively etched relative to the second or first semiconductor, respectively, fabrication, on a part of the stack, of external spacers and at least one dummy gate, etching of the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, after the etching of the stack, thermal treatment of the stack of nanowires.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Applicants: Commissariat A L'Energle A.tomique et aux Energies Alternatives, International Business Machines Corporation
    Inventors: Shay REBOH, Kangguo CHENG, Remi COQUAND, Nicolas LOUBET
  • Publication number: 20200111872
    Abstract: Production of a structure for a transistor, with semiconductor bars disposed one above the other and able to form at least one transistor channel region, the method comprising growth of a semiconductor material around semiconductor bars disposed one above the other, while, during this growth, preserving a dummy bar situated above the semiconductor bars in order to limit the thickness of semiconductor material formed and/or to make this thickness uniform from one bar to another.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Shay REBOH, Remi Coquand
  • Publication number: 20200098859
    Abstract: A method for making first and second superimposed transistors, including: making, on a substrate, a stack of several semiconducting nanowires; etching a first nanowire so that a remaining portion of the first nanowire forms a channel of the first transistor; etching a second nanowire arranged between the substrate and the first nanowire, so that a remaining portion of the second nanowire forms a channel of the second transistor and has a greater length than that of the remaining portion of the first nanowire; making second source and drain regions in contact with ends of the remaining portion of the second nanowire; depositing a first dielectric encapsulation layer covering the second source and drain regions and forming vertical insulating portions; making first source and drain regions in contact with ends of the remaining portion of the first nanowire and insulated from the second source and drain regions by the vertical insulating portions.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 26, 2020
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, International Business Machines Corporation
    Inventors: Shay Reboh, Remi Coquand, Nicolas Loubet, Tenko Yamashita, Jingyun Zhang
  • Publication number: 20200058768
    Abstract: A method of fabricating a double gate structure for transistors with superposed bars is provided, including: providing, on a support, a stack including an alternation of one or several first bars made of a first semiconducting material, and one or several second bars based on a second semiconducting material; removing lateral portions of the second bars; forming insulating plugs in contact with lateral regions of the second bars; removing the first bars; and forming a gate electrode facing an upper face and a lower face of the second bars, the insulating plugs being arranged in contact with the lateral regions of the second bars when the gate electrode is being formed.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 20, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi COQUAND, Shay REBOH
  • Patent number: 10553723
    Abstract: A method is provided of fabricating a microelectronic device including a semiconductor structure provided with semiconductor bars positioned above one another, the method including the following steps: creating, on a substrate, a stacked structure including an alternation of first bars containing a first material and having a first critical dimension and second bars containing a second material, the second material being a semiconductor, the second bars having a second critical dimension greater than the first critical dimension, then, surface doping protruding lateral portions of the second bars before forming a source and drain block on the portions.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: February 4, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Remi Coquand, Nicolas Loubet, Shay Reboh, Robin Chao
  • Publication number: 20200027791
    Abstract: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
    Type: Application
    Filed: July 18, 2018
    Publication date: January 23, 2020
    Inventors: Nicolas Loubet, Emmanuel Augendre, Remi Coquand, Shay Reboh