Patents by Inventor Renu Whig
Renu Whig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9391264Abstract: An MRAM bit includes a free magnetic region, a fixed magnetic region comprising an anti-ferromagnetic material, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, (ii) a second layer of one or more ferromagnetic materials wherein the one or more ferromagnetic materials includes cobalt, (iii) a third layer of one or more ferromagnetic materials, and an anti-ferromagnetic coupling layer, wherein: (a) the anti-ferromagnetic coupling layer is disposed between the first and third layers, and (b) the second layer is disposed between the first layer and the anti-ferromagnetic coupling layer.Type: GrantFiled: June 2, 2015Date of Patent: July 12, 2016Assignee: Everspin Technologies, Inc.Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
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Publication number: 20160172582Abstract: A magnetoresistive memory array including a plurality of magnetoresistive memory elements wherein each magnetoresistive memory element comprises a free layer including at least one ferromagnetic layer having perpendicular magnetic anisotropy, a fixed layer, and a tunnel barrier, disposed between and in contact with the free and fixed layers. The tunnel barrier includes a first metal-oxide layer, having a thickness between 1 and 10 Angstroms, a second metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed on the first metal-oxide layer, and a third metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed over the second metal-oxide layer. In one embodiment, the third metal-oxide layer is in contact with the free layer or fixed layer. The tunnel barrier may also include a fourth metal-oxide layer, having a thickness between 1 and 10 Angstroms, disposed between the second and third metal-oxide layers.Type: ApplicationFiled: February 15, 2016Publication date: June 16, 2016Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
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Publication number: 20160163964Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.Type: ApplicationFiled: February 18, 2016Publication date: June 9, 2016Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
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Patent number: 9362491Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.Type: GrantFiled: November 30, 2015Date of Patent: June 7, 2016Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
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Publication number: 20160104835Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.Type: ApplicationFiled: November 30, 2015Publication date: April 14, 2016Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu WHIG, Phillip MATHER, Kenneth SMITH, Sanjeev AGGARWAL, Jon SLAUGHTER, Nicholas RIZZO
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Patent number: 9293698Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.Type: GrantFiled: May 1, 2015Date of Patent: March 22, 2016Assignee: Everspin Technologies, Inc.Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
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Patent number: 9269891Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.Type: GrantFiled: August 21, 2013Date of Patent: February 23, 2016Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu Whig, Philip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
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Publication number: 20160013401Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.Type: ApplicationFiled: September 21, 2015Publication date: January 14, 2016Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
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Patent number: 9159906Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.Type: GrantFiled: March 19, 2014Date of Patent: October 13, 2015Assignee: Everspin Technologies, Inc.Inventors: Renu Whig, Jon Slaughter, Nicholas Rizzo, Jijun Sun, Frederick Mancoff, Dimitri Houssameddine
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Publication number: 20150280110Abstract: An MRAM bit includes a free magnetic region, a fixed magnetic region comprising an anti-ferromagnetic material, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, (ii) a second layer of one or more ferromagnetic materials wherein the one or more ferromagnetic materials includes cobalt, (iii) a third layer of one or more ferromagnetic materials, and an anti-ferromagnetic coupling layer, wherein: (a) the anti-ferromagnetic coupling layer is disposed between the first and third layers, and (b) the second layer is disposed between the first layer and the anti-ferromagnetic coupling layer.Type: ApplicationFiled: June 2, 2015Publication date: October 1, 2015Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
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Patent number: 9136464Abstract: An MRAM device, and a process for manufacturing the device, provides improved breakdown distributions, a reduced number of bits with a low breakdown voltage, and an increased MR, thereby improving reliability, manufacturability, and error-free operation. A tunnel barrier is formed between a free layer and a fixed layer in three repeating steps of forming a metal material, interceded by oxidizing each of the metal materials. The oxidization of the third metal material is greater than the dose of the first metal, but less than the dose of the second metal. The fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.Type: GrantFiled: September 25, 2013Date of Patent: September 15, 2015Assignee: Everspin Technologies, Inc.Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
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Publication number: 20150236253Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.Type: ApplicationFiled: May 1, 2015Publication date: August 20, 2015Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
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Patent number: 9093637Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.Type: GrantFiled: June 12, 2014Date of Patent: July 28, 2015Assignee: Everspin Technologies, Inc.Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
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Publication number: 20150021606Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.Type: ApplicationFiled: June 12, 2014Publication date: January 22, 2015Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason Janesky, Nicholas D. Rizzo, Jon Slaughter
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Publication number: 20140217528Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.Type: ApplicationFiled: March 19, 2014Publication date: August 7, 2014Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu Whig, Jon Slaughter, Nicholas Rizzo, Jijun Sun, Frederick Mancoff, Dimitri Houssameddine
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Patent number: 8754460Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.Type: GrantFiled: June 24, 2013Date of Patent: June 17, 2014Assignee: EverSpin Technologies, Inc.Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
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Publication number: 20140159179Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.Type: ApplicationFiled: January 30, 2014Publication date: June 12, 2014Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Jijun Sun, Phillip Mather, Srinivas Pietambaram, Jon Slaughter, Renu Whig, Nicholas Rizzo
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Publication number: 20140138346Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.Type: ApplicationFiled: August 21, 2013Publication date: May 22, 2014Applicant: EverSpin Technologies, Inc.Inventors: Renu Whig, Philip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
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Patent number: 8686484Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.Type: GrantFiled: June 10, 2011Date of Patent: April 1, 2014Assignee: EverSpin Technologies, Inc.Inventors: Renu Whig, Jon Slaughter, Nicholas Rizzo, Jijun Sun, Frederick Mancoff, Dimitri Houssameddine
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Patent number: 8647891Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.Type: GrantFiled: June 4, 2013Date of Patent: February 11, 2014Assignee: Everspin Technologies, Inc.Inventors: Jijun Sun, Phillip Mather, Srinivas Pietambaram, Jon Slaughter, Renu Whig, Nicholas Rizzo