Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.

Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.

Abstract: A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.

Abstract: An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.

Abstract: In one implementation, a memory module with on-die error correction code (ECC) with scrub operation capabilities and a programmable patrol scrub period is coupled to a memory controller that causes error correction operations to perform based on a power status of an energy storage device.

Abstract: Designing a circuit apparatus involves determining locations and lengths of routing paths for signals, routing paths of a first length range being located in a first layer, and routing paths of a second length range being located in a second layer; determining propagation speeds for the signals to propagate through the routing paths within a propagation time range; and selecting dielectric materials for the layers in accordance with the determined propagation speeds for the routing paths.

Abstract: A method includes querying a memory to determine what type of voltage the memory requires and applying the proper operating voltage to the memory based on the query. An apparatus that supports different memory types is also disclosed.

Abstract: In at least some embodiments, a system comprises a processor and a memory coupled to the processor. The memory stores processor performance utility instructions and performance adjustment instructions. When executed, the processor performance utility instructions are configured to cause activities of the processor to be counted and to cause a processor utilization value to be determined based on the counts. When executed, the performance adjustment instructions are configured to adjust the processor utilization value based on a comparison of the processor's current operating frequency and maximum operating frequency.

Abstract: A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation speed different from the first propagation speed.

Abstract: Noise reduction methods and systems are described. In one embodiment, a user location system is configured to determine a user's location within a room. A noise profile processing unit is configured to produce a remedial noise profile specific to the user's location for use in reducing user-perceivable noise at the user's location.

Abstract: A computer system determines whether a voltage signal that powers a slot circuitry and a card in one of two modes has been properly generated. If so, then the slot circuitry and the card are initialized in the one mode. Otherwise, the slot circuitry and the card are initialized in the other of the two modes.

Abstract: In at least some embodiments, a computer system comprises a central processing unit (“CPU”), a bridge device coupled to a main memory, and a cache controller coupled between the bridge device and the CPU. The computer system further comprises a cache memory coupled to the cache controller and providing memory space to the CPU, wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using a first protocol and the bridge device communicates using a second protocol, and wherein the cache controller allows communication between the CPU and the bridge device when the CPU communicates using the second protocol and the bridge device communicates using the first protocol.