Abstract: A modular interconnectivity assembly for interconnecting elements of a point of sale system, the modular interconnectivity assembly including at least one interconnectivity module including an Input/Output (I/O) hub having at least one upstream facing port and at least two downstream facing ports, at least one upstream connector connected to the at least one upstream facing port of the (I/O) hub and adapted for communication in accordance with a first communication protocol, at least one downstream connector connected to at least one of the at least two downstream facing ports and adapted for communication in accordance with the first communication protocol and at least one interface connected to another of the at least two downstream facing ports and adapted for communication in accordance with a second communication protocol, different from the first communication protocol.

Abstract: A modular interconnectivity assembly for interconnecting elements of a point of sale system, the modular interconnectivity assembly including at least one interconnectivity module including an Input/Output (I/O) hub having at least one upstream facing port and at least two downstream facing ports, at least one upstream connector connected to the at least one upstream facing port of the (I/O) hub and adapted for communication in accordance with a first communication protocol, at least one downstream connector connected to at least one of the at least two downstream facing ports and adapted for communication in accordance with the first communication protocol and at least one interface connected to another of the at least two downstream facing ports and adapted for communication in accordance with a second communication protocol, different from the first communication protocol.

Abstract: A closed-loop controller of an apparatus in an example operates a set of switches to dynamically configure power rails to an industry-standard socket.

Abstract: A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank.

Abstract: A system (100, 500, 600, 800) of ink and multi-channel data delivery includes an optically transmissive tubular body (113) having at least two ends (105, 107). The tubular body (113) defines an ink channel between an ink supply (101) and at least one inkjet pen (117, 521, 525, 529, 901, 903). A multi-channel optical transmitter (111, 300, 400) is in optical communication with one end (105, 107) of the tubular body (113), and an optical receiver (115, 509, 511, 513) is in optical communication with another end (105, 107) of the tubular body (113).

Abstract: A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).

Abstract: A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).

Abstract: A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs) through employment of a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol).

Abstract: A translator of an apparatus in an example communicatively interconnects a serial protocol bus that follows a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) and three or more parallel protocol memory module channels that comprise a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

Abstract: A modular DIMM carrier and riser slot device includes a slot section having a slot configured to hold a plurality of memory device planars, a first latch disposed at a first end of the slot section and pivotably connected to the slot section and capable of securing a first end of the memory device planars; a second latch disposed at a second end of the slot section and pivotably connected to the slot section and capable of securing a second end of a first memory device planar, and a third latch pivotably connected to the slot section and disposed intermediate between the first and the second latches, the third latch capable of securing a second end of a second memory device planar. The slot section has an auxiliary slot section defined as an section between the second latch and the third latch.

Abstract: A translator of an apparatus in an example employs a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) to write to a plurality of parallel protocol memory module channels that comprises a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

Abstract: A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank.

Abstract: Attachment mechanisms are surface-mounted to a PC board. An object is secured relative to said PC board by a retention device attached to the attachment mechanisms.

Abstract: In one embodiment, the invention recites a fan motor assembly with integrated redundant availability. The fan motor assembly comprises a fan motor subassembly with a plurality of replaceable fan motors, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively engages one of the plurality of replaceable fan motors to a fan. The fan motor assembly further comprises a control unit which is coupled to the fan motor selector mechanism which is configured to control the fan motor selector mechanism such that a first replaceable fan motor mechanically powers the fan while a second replaceable fan motor can be dynamically removed from the fan motor subassembly.

Abstract: A fan motor assembly with integrated redundant availability is recited. The fan motor assembly can include a fan motor subassembly with a first fan motor and a second fan motor, and a fan motor selector mechanism coupled to the fan motor subassembly, so that the fan motor selector mechanism selectively couples the first fan motor or second fan motor to a fan. The fan motor assembly can also include a control unit coupled to the fan motor selector mechanism, wherein the control unit is configured to control the fan motor selector mechanism such that either of the first fan motor and second fan motor is selectively engaged to the fan.