Patents by Inventor Ricardo Pureza Coimbra
Ricardo Pureza Coimbra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11043893Abstract: A bias circuit is provided. The bias circuit includes a comparator circuit configured to compare a first voltage at a first input with a second voltage at a second input and generate a digital value at an output. A level shifter circuit is coupled to the comparator circuit. The level shifter is configured to receive a reference voltage at an input and generate the second voltage at an output. A charge pump circuit is coupled to the comparator circuit. The charge pump circuit is configured to generate the first voltage at an output based on the digital value.Type: GrantFiled: May 27, 2020Date of Patent: June 22, 2021Assignee: NXP USA, INC.Inventors: Marcos Mauricio Pelicia, Ricardo Pureza Coimbra, Luis Enrique Del Castillo, Eduardo Ribeiro da Silva
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Patent number: 10819279Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain control stage, a filter stage, and an output stage. The gain control stage includes an input coupled at a first oscillator terminal configured and arranged for connection to a first terminal of a crystal. The filter stage includes an input coupled to an output of the gain control stage. The output stage includes a first transistor having a first current electrode coupled at a second oscillator terminal configured and arranged for connection to a second terminal of the crystal and a control electrode coupled to receive a voltage signal at the first oscillator terminal and a first bias voltage.Type: GrantFiled: June 28, 2019Date of Patent: October 27, 2020Assignee: NXP USA, INC.Inventors: Juan Camilo Monsalve, Ricardo Pureza Coimbra, James Robert Feddeler, Stefano Pietri
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Patent number: 10712210Abstract: A sensor may include: a first plurality of resistors; a first BJT having: a first base terminal, a collector terminal, and an emitter terminal, where the collector terminal is coupled to the first plurality of resistors; and a first amplifier having a first non-inverting input coupled to the collector terminal and an output terminal coupled to the base terminal. The sensor may include: a second plurality of resistors; a second BJT having: a base terminal, a collector terminal, and an emitter terminal, where the base terminal is coupled to the base terminal of the first BJT, where the collector terminal is coupled to the second plurality of resistors; and a second amplifier having an inverting input coupled to the collector terminal and an output terminal coupled to the emitter terminal, wherein the inverting input terminal of the first amplifier is coupled to a non-inverting input terminal of the second amplifier.Type: GrantFiled: December 29, 2017Date of Patent: July 14, 2020Assignee: NXP USA, Inc.Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, Jr.
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Publication number: 20200173862Abstract: An embodiment for an integrated circuit for temperature detection includes: a closed loop circuit branch including: a first bipolar junction transistor (BJT), a first resistor coupled between a first base of the first BJT and a junction node, and an amplifier having an output coupled to the junction node and a non-inverting input coupled to a collector of the first BJT; and an open loop circuit branch including: a second BJT, a second resistor coupled between a base of the second BJT and the junction node, a third resistor coupled between the base of the second BJT and ground, and a comparator having an inverting input coupled to a collector of the second BJT and an output configured to provide a digital voltage signal that corresponds to a temperature reading.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Inventors: Ricardo Pureza COIMBRA, Juan Camilo Monsalve
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Patent number: 10658927Abstract: Regulation systems and methods use a first regulator and a tracking second regulator. The first regulator receives a reference voltage and generates a first voltage output based upon the reference voltage, which is coupled as a back-bias voltage to a first load region within the integrated circuit. The first regulator also receives a sampled version of the first voltage output as feedback. A second regulator receives the first sampled voltage output and generates a second voltage output. The second regulator also receives a sampled version of the second voltage output as feedback. During operation, the second voltage output tracks (e.g., by a symmetry ratio) the first voltage output and is coupled as a back-bias voltage to a second load region within the integrated circuit. Further, switched-capacitor operation can be implemented, and clock frequency can be adjusted based upon the first sampled voltage output to reduce power consumption.Type: GrantFiled: April 30, 2019Date of Patent: May 19, 2020Assignee: NXP USA, Inc.Inventors: Marcos Mauricio Pelicia, Ricardo Pureza Coimbra, Luis Enrique Del Castillo, Lei Tian
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Patent number: 10429879Abstract: An embodiment for bandgap reference voltage circuitry includes: a bandgap reference voltage generator including: a first bipolar junction transistor (BJT); a first amplifier having a non-inverting input coupled to a collector of the first BJT and a first output node configured to provide a bandgap reference voltage; a first resistor coupled between a base of the first BJT and the first output node; a second BJT; a second amplifier having a non-inverting input coupled to a collector of the second BJT and a second output node coupled to a junction node; a second resistor coupled between a base of the second BJT and the junction node; and a third resistor coupled between the base of the first BJT and the junction node.Type: GrantFiled: December 4, 2018Date of Patent: October 1, 2019Assignee: NXP USA, Inc.Inventor: Ricardo Pureza Coimbra
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Patent number: 10394264Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.Type: GrantFiled: February 9, 2018Date of Patent: August 27, 2019Assignee: NXP USA, Inc.Inventors: Ricardo Pureza Coimbra, Javier Mauricio Olarte Gonzalez, Ivan Carlos Ribeiro do Nascimento, Felipe Ricardo Clayton, Stefano Pietri, Charles Eric Seaberg
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Publication number: 20190250656Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.Type: ApplicationFiled: February 9, 2018Publication date: August 15, 2019Inventors: Ricardo Pureza Coimbra, Javier Mauricio Olarte Gonzalez, Ivan Carlos Ribeiro do Nascimento, Felipe Ricardo Clayton, Stefano Pietri, Charles Eric Seaberg
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Publication number: 20190204164Abstract: A sensor may include: a first plurality of resistors; a first BJT having: a first base terminal, a collector terminal, and an emitter terminal, where the collector terminal is coupled to the first plurality of resistors; and a first amplifier having a first non-inverting input coupled to the collector terminal and an output terminal coupled to the base terminal. The sensor may include: a second plurality of resistors; a second BJT having: a base terminal, a collector terminal, and an emitter terminal, where the base terminal is coupled to the base terminal of the first BJT, where the collector terminal is coupled to the second plurality of resistors; and a second amplifier having an inverting input coupled to the collector terminal and an output terminal coupled to the emitter terminal, wherein the inverting input terminal of the first amplifier is coupled to a non-inverting input terminal of the second amplifier.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, JR.
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Patent number: 9641129Abstract: A resistor-less amplifying circuit includes a plurality of resistor-less cells. Each cell includes a plurality of MOS transistors. Each cell generates a differential output equal to ?VGS of two MOS transistors with a magnitude of the differential output controlled by a control voltage generated by a differential amplifier coupled to a feedback loop around a cell. In one embodiment, the resistor-less amplifying circuit is a part of a bandgap voltage reference circuit. In another embodiment, the resistor-less amplifying circuit is part of a temperature sensor circuit.Type: GrantFiled: September 16, 2015Date of Patent: May 2, 2017Assignee: NXP USA, Inc.Inventors: Ricardo Pureza Coimbra, André Luis Vilas Boas, Alfredo Olmos
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Publication number: 20170077872Abstract: A resistor-less amplifying circuit includes a plurality of resistor-less cells. Each cell includes a plurality of MOS transistors. Each cell generates a differential output equal to ?VGS of two MOS transistors with a magnitude of the differential output controlled by a control voltage generated by a differential amplifier coupled to a feedback loop around a cell. In one embodiment, the resistor-less amplifying circuit is a part of a bandgap voltage reference circuit. In another embodiment, the resistor-less amplifying circuit is part of a temperature sensor circuit.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Ricardo Pureza COIMBRA, André Luis VILAS BOAS, Alfredo OLMOS
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Patent number: 9074943Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.Type: GrantFiled: October 30, 2012Date of Patent: July 7, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, Jr., Pedro B. Zanetta
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Patent number: 8890612Abstract: A transconductance amplification stage (301) includes a differential pair (306) wherein a bias current flows through each transistor (302, 304) of the pair when input voltages are equal. Tail current boosting circuitry (320), which includes a tail transistor, provides a translinear expansion of tail current of the differential pair. A feedback loop (307) dynamically biases the differential pair to maintain current through one transistor (302) of the pair at the bias current value in spite of a difference between input voltages. Another transistor (304) of the pair provides an output current responsive to a difference between input voltages. The output current is not affected by a region of operation of the tail transistor. An output structure (300, 500) includes the transconductance amplification stage and a circuit (303) for mirroring the output current. An amplifier (800) includes the output structure as a buffer between other structures (801) and an output terminal.Type: GrantFiled: October 19, 2012Date of Patent: November 18, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, Jr.
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Publication number: 20140111278Abstract: A transconductance amplification stage (301) includes a differential pair (306) wherein a bias current flows through each transistor (302, 304) of the pair when input voltages are equal. Tail current boosting circuitry (320), which includes a tail transistor, provides a translinear expansion of tail current of the differential pair. A feedback loop (307) dynamically biases the differential pair to maintain current through one transistor (302) of the pair at the bias current value in spite of a difference between input voltages. Another transistor (304) of the pair provides an output current responsive to a difference between input voltages. The output current is not affected by a region of operation of the tail transistor. An output structure (300, 500) includes the transconductance amplification stage and a circuit (303) for mirroring the output current. An amplifier (800) includes the output structure as a buffer between other structures (801) and an output terminal.Type: ApplicationFiled: October 19, 2012Publication date: April 24, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ricardo Pureza COIMBRA, Edevaldo PEREIRA da SILVA, JR.
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Patent number: 8378735Abstract: A die temperature sensor circuit (200) includes an amplifier (203) that has first and second stages of amplification and that has bipolar transistors (201 and 202) as an input differential pair. The bipolar transistors have different current densities. A difference between base-emitter voltages of the bipolar transistors is proportional to absolute temperature of the bipolar transistors. The bipolar transistors also provide amplification for the first stage of amplification. Multiple feedback loops maintain a same ratio between the current densities of the bipolar transistors over temperature by changing collector currents that bias the bipolar transistors. A feedback loop includes a second stage of amplification and such feedback loop cancels effect that base currents of the bipolar transistors have on an output signal of the die temperature sensor circuit.Type: GrantFiled: November 29, 2010Date of Patent: February 19, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Edevaldo Pereira Da Silva, Jr., Ricardo Pureza Coimbra
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Publication number: 20120133422Abstract: A die temperature sensor circuit (200) includes an amplifier (203) that has first and second stages of amplification and that has bipolar transistors (201 and 202) as an input differential pair. The bipolar transistors have different current densities. A difference between base-emitter voltages of the bipolar transistors is proportional to absolute temperature of the bipolar transistors. The bipolar transistors also provide amplification for the first stage of amplification. Multiple feedback loops maintain a same ratio between the current densities of the bipolar transistors over temperature by changing collector currents that bias the bipolar transistors. A feedback loop includes a second stage of amplification and such feedback loop cancels effect that base currents of the bipolar transistors have on an output signal of the die temperature sensor circuit.Type: ApplicationFiled: November 29, 2010Publication date: May 31, 2012Applicant: Freescale Semiconductor, Inc.Inventors: Edevaldo Pereira da Silva, JR., Ricardo Pureza Coimbra