Patents by Inventor Riccardo Gemelli
Riccardo Gemelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240098566Abstract: Systems, methods, and software for load management among a plurality of cells that overlap a sector within a Radio Access Network (RAN). In one embodiment, a system receives, at a machine learning system, input data for a sector of the RAN having a plurality of cells overlapping at the sector. The system processes the input data at the machine learning system to determine recommended load distribution parameters for the sector based on a machine learning model, where the recommended load distribution parameters are configured to maximize an aggregated user throughput of the sector. The system applies the recommended load distribution parameters in the sector to distribute users among the cells.Type: ApplicationFiled: January 19, 2021Publication date: March 21, 2024Inventors: Riccardo GEMELLI, Giuliano CORBETTA, Marco PISCHEDDA, Reinhard VOESE
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Publication number: 20240089781Abstract: Systems, methods, and software for load management among a plurality of cells that overlap a sector within a Radio Access Network (RAN). In one embodiment, a system performs sector throughput optimization over multiple optimization iterations of determining a total number of active users in the sector, determining a target number of users per cell that maximizes an aggregated user throughput of the sector where a sum of the target number of users per cell is equal to the total number of active users in the sector, determining recommended load distribution parameters for the sector based on the target number of users per cell that maximizes the aggregated user throughput of the sector, and applying the recommended load distribution parameters in the sector to distribute users among the cells.Type: ApplicationFiled: January 19, 2021Publication date: March 14, 2024Inventors: Riccardo GEMELLI, Giuliano CORBETTA, Marco PISCHEDDA, Reinhard VOESE
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Patent number: 11463720Abstract: A method, includes: storing at least one set of data in a memory space, wherein the at least one set of data stored has a memory footprint in the memory space; and coupling, to the at least one set of data, a respective counter indicative of the at least one set of data, wherein the respective counter is embedded in the at least one set of data without increasing the memory footprint in the memory space.Type: GrantFiled: September 26, 2018Date of Patent: October 4, 2022Assignee: STMicroelectronics S.r.l.Inventors: Nicola Marinelli, Riccardo Gemelli
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Patent number: 11436162Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.Type: GrantFiled: May 22, 2020Date of Patent: September 6, 2022Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l., STMicroelectronics International N.V.Inventors: Riccardo Gemelli, Denis Dutey, Om Ranjan
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Patent number: 11055173Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: GrantFiled: December 4, 2019Date of Patent: July 6, 2021Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Patent number: 10860415Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: GrantFiled: June 27, 2019Date of Patent: December 8, 2020Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
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Publication number: 20200379924Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.Type: ApplicationFiled: May 22, 2020Publication date: December 3, 2020Inventors: Riccardo Gemelli, Denis Dutey, Om Ranjan
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Publication number: 20200110663Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: ApplicationFiled: December 4, 2019Publication date: April 9, 2020Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om RANJAN, Riccardo GEMELLI, Denis DUTEY
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Patent number: 10528422Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: GrantFiled: November 13, 2017Date of Patent: January 7, 2020Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Grenoble 2) SASInventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Publication number: 20190317851Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: ApplicationFiled: June 27, 2019Publication date: October 17, 2019Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om RANJAN, Riccardo GEMELLI, Abhishek GUPTA
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Patent number: 10379937Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: GrantFiled: October 31, 2017Date of Patent: August 13, 2019Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
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Publication number: 20190146868Abstract: Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.Type: ApplicationFiled: November 13, 2017Publication date: May 16, 2019Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SASInventors: Om Ranjan, Riccardo Gemelli, Denis Dutey
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Publication number: 20190129790Abstract: A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicants: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Om Ranjan, Riccardo Gemelli, Abhishek Gupta
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Publication number: 20190098327Abstract: A method, includes: storing at least one set of data in a memory space, wherein the at least one set of data stored has a memory footprint in the memory space; and coupling, to the at least one set of data, a respective counter indicative of the at least one set of data, wherein the respective counter is embedded in the at least one set of data without increasing the memory footprint in the memory space.Type: ApplicationFiled: September 26, 2018Publication date: March 28, 2019Inventors: Nicola Marinelli, Riccardo Gemelli
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Patent number: 9203725Abstract: It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.Type: GrantFiled: April 14, 2011Date of Patent: December 1, 2015Assignee: Alcatel LucentInventors: Luigi Ronchetti, Riccardo Gemelli, Giorgio Cazzaniga, Carlo Costantini
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Patent number: 9154446Abstract: A network element for a digital transmission network is proposed. The network element contains two switching matrices for switching data cells, as well as ingress ports that receive TDM traffic flow and packet traffic flow and segment the traffic flows into cells. A control system for controlling the configuration of the ingress ports and the switching matrices controls the ingress ports, in case of no failure of the switching matrices, to forward the TDM traffic flows to both switching matrices and to split the packet traffic flow over the two switching matrices.Type: GrantFiled: September 28, 2011Date of Patent: October 6, 2015Assignee: Alcatel LucentInventors: Riccardo Gemelli, Luigi Ronchetti, Andrea Paparella, Vincenzo Sestito
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Patent number: 8594136Abstract: There is described a method for transmitting N parallel data flows on a parallel bus. The method comprises, at a first communication device: generating a further parallel data flow comprising alignment words periodically distributed with a period; at each period, rotating the N of parallel data flows and the further parallel data flow thus generating N+1 rotated parallel data flows, each comprising part of the alignment words periodically distributed with a frame period; transmitting the N+1 rotated parallel data flows on respective physical connections of the parallel bus. The method further comprises, at a second communication device: aligning the N+1 rotated parallel data flows by using the alignment words, thus compensating skew and obtaining N+1 aligned parallel data flows; and at each period, de-rotating the N+1 aligned parallel data flows, thus generating N de-rotated parallel data flows corresponding to the N parallel data flows.Type: GrantFiled: December 11, 2009Date of Patent: November 26, 2013Assignee: Alcatel LucentInventors: Silvio Cucchi, Riccardo Gemelli, Luigi Ronchetti
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Publication number: 20130182716Abstract: A network element for a digital transmission network is proposed. The network element contains two switching matrices for switching data cells, as well as ingress ports that receive TDM traffic flow and packet traffic flow and segment the traffic flows into cells. A control system for controlling the configuration of the ingress ports and the switching matrices controls the ingress ports, in case of no failure of the switching matrices, to forward the TDM traffic flows to both switching matrices and to split the packet traffic flow over the two switching matrices.Type: ApplicationFiled: September 28, 2011Publication date: July 18, 2013Inventors: Riccardo Gemelli, Luigi Ronchetti, Andrea Pararella, Vincenzo Sestito
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Patent number: 8429511Abstract: Equipment protection of a switch matrix (SM) in a network node, which contains a number of matrix modules (M1.1-M4.4, E1.5-E4.6) is achieved by slicing an input signal into k parallel signal slices (x(0)-x(3)) with k>2; coding the k signal slices into a number of n coded signal slices (x(0)-x(5)) with n>k+1 using an error correcting code to add redundancy to said input signal; switching said n coded signal slices through the switching matrix (SM) via n distinct matrix modules; and decoding the n coded signal slices into k decoded signal slices to correct errors introduced while passing through said switch matrix. Preferably, the switch matrix (SM) contains a first number of matrix boards (MB1-MB4, EB5, EB6), each carrying a second number of matrix modules (M1.1-M4.4, E1.5-E4.6). The n coded signal slices are switched via matrix modules on n distinct matrix boards.Type: GrantFiled: November 18, 2009Date of Patent: April 23, 2013Assignee: Alcatel LucentInventors: Silvio Cucchi, Giuseppe Badalucco, Carlo Costantini, Riccardo Gemelli, Luigi Ronchetti
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Publication number: 20130028265Abstract: It is disclosed a method for updating a cumulative residence time of a synchronization packet received at a node of a packet-switched communication network. The cumulative residence time is equal to a cumulative sum of residence times of the packet at nodes interposed between a further node which has generated the packet and the node. The node comprises an ingress circuit and an egress circuit. The method comprises: receiving the packet at the egress circuit from the ingress circuit; at a timestamp generator of the egress circuit, generating a timestamp; at the egress circuit, calculating a virtual timestamp based on the timestamp and on an estimated variable delay that will be undergone by the packet due to buffering in a buffer located downstream the timestamp generator; and, at the egress circuit, using the virtual timestamp for updating the cumulative residence time, before transmitting the packet to a still further node.Type: ApplicationFiled: April 14, 2011Publication date: January 31, 2013Inventors: Luigi Ronchetti, Riccardo Gemelli, Giorgio Cazzaniga, Carlo Costantini