Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: Implementations of image sensors may include a passivation layer coupled over a silicon layer, a color-filter-array coupled over the passivation layer, a lens coupled over the color-filter-array, and at least two optically transmissive charge dissipation layers coupled over the silicon layer.

Abstract: An image sensor may include pixels having nested sub-pixels. A pixel with nested sub-pixels may include an inner sub-pixel that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group that includes one or more sub-pixels. The inner sub-pixel may have a light collecting area at a surface that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group to the outer sub-pixel groups in nested sub-pixels. A color filter of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.

Abstract: An image sensor may include pixels having nested sub-pixels. A pixel with nested sub-pixels may include an inner sub-pixel that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group that includes one or more sub-pixels. The inner sub-pixel may have a light collecting area at a surface that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group to the outer sub-pixel groups in nested sub-pixels. A color filter of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.

Abstract: Various embodiments of the present technology may comprise a method and device for a multi-branch transistor for use in an image sensor. The device may comprise an active region, wherein the active region comprises three doped regions. At least two of the three doped region may be floating diffusion active regions, wherein each floating diffusion active region is connected to a single photosensitive element or multiple photosensitive elements. The device may comprise a multi-branch channel region defined by the area underlying a gate region and substantially surrounded by the doped regions.

Abstract: An image sensor may include pixels having nested sub-pixels. A pixel with nested sub-pixels may include an inner sub-pixel that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group that includes one or more sub-pixels. The inner sub-pixel may have a light collecting area at a surface that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group to the outer sub-pixel groups in nested sub-pixels. A color filter of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.

Abstract: Various embodiments of the present technology may comprise a method and device for a multi-branch transistor for use in an image sensor. The device may comprise an active region, wherein the active region comprises three doped regions. At least two of the three doped region may be floating diffusion active regions, wherein each floating diffusion active region is connected to a single photosensitive element or multiple photosensitive elements. The device may comprise a multi-branch channel region defined by the area underlying a gate region and substantially surrounded by the doped regions.

Abstract: An image sensor with an array of pixels is provided. The array may include a semiconductor substrate having opposing first and second sides. A first photodiode region may be implanted in the semiconductor substrate through the first side. A second photodiode region may be implanted in the semiconductor substrate through the second side. The second photodiode region may be implanted to overlap with the first photodiode region in the semiconductor substrate to form a continuous photodiode region that extends from the first side to the second side of the substrate. The continuous region may generate charge in response to image light. The continuous region may belong to a single pixel that generates an image signal from the charge. The image signal may be conveyed to readout circuitry via metallization layers formed over the substrate. The first and second photodiode regions may be thermally activated prior to forming the metallization layers.

Abstract: An image sensor may include an array of photodiodes and readout circuitry. A group of adjacent photodiodes in the array may be covered with a first color filter element that transmits a first color light and an additional group of adjacent photodiodes may be covered with a second color filter element that transmits a second color light. The group of photodiodes may share a floating diffusion node. The array may be operable in a low resolution mode in which the readout circuitry reads out image signals corresponding to a sum of charges generated by the group of photodiodes and in a high resolution mode in which the readout circuitry reads out image signals corresponding to charges generated by each of the photodiodes from the shared floating diffusion node. The photodiodes in the group may capture charge using different integration times for generating high-dynamic-range images.

Abstract: Various embodiments of the present technology may comprise a method and device for a multi-source/drain transistor for use in an image sensor. The device may comprise an active region, wherein the active region comprises three doped regions. Two of the three doped region may be floating diffusion active regions, wherein each floating diffusion active region is connected to a photosensitive element. The device may comprise a multi-branch channel defined by the area underlying a gate region and substantially surrounded by the doped regions. During operation the electron path may form an “L” shape within the channel.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for a pixel array. Each pixel may include multiple storage regions capable of storing pixel signals during integration. The method and apparatus may utilize the floating diffusion region as a storage region during both an integration period and readout period. The method and apparatus may store pixel signals corresponding to a first exposure periods in the floating diffusion region and pixel signals corresponding to a second exposure periods in a separate storage region.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for a pixel array. Each pixel may include multiple storage regions capable of storing pixel signals during integration. The method and apparatus may utilize the floating diffusion region as a storage region during both an integration period and readout period. The method and apparatus may store pixel signals corresponding to a first exposure periods in the floating diffusion region and pixel signals corresponding to a second exposure periods in a separate storage region.

Abstract: A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery of the array of pixels may be recessed into a back surface of the substrate. The bond pads may be recessed into a semiconductor layer of the substrate, may be recessed into a window in the semiconductor layer, or may be recessed in a passivation layer and covered with non-conductive material such as resin. In order to further improve surface planarity, a window may be formed in the semiconductor layer at the periphery of the array of pixels, or scribe region, over alignment structures. By providing an image sensor with improved surface planarity, device yield and time-to-market may be improved, and window framing defects and microlens/color filter non-uniformity may be reduced.

Abstract: A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

Abstract: An image sensor with an array of pixels is provided. The array may include a semiconductor substrate having opposing first and second sides. A first photodiode region may be implanted in the semiconductor substrate through the first side. A second photodiode region may be implanted in the semiconductor substrate through the second side. The second photodiode region may be implanted to overlap with the first photodiode region in the semiconductor substrate to form a continuous photodiode region that extends from the first side to the second side of the substrate. The continuous region may generate charge in response to image light. The continuous region may belong to a single pixel that generates an image signal from the charge. The image signal may be conveyed to readout circuitry via metallization layers formed over the substrate. The first and second photodiode regions may be thermally activated prior to forming the metallization layers.

Abstract: An image sensor may include an array of image photodiodes formed in rows and columns. The array of image photodiodes may include a region of photodiodes arranged in three adjacent rows and three adjacent columns of the array. The region of photodiodes may include four non-adjacent photodiodes, each of which generates charge in response to the same color of light. The four non-adjacent photodiodes may be coupled to a shared floating diffusion node. Each of the four non-adjacent photodiodes may transfer generated charge to the shared floating diffusion node. The charges from each of the four non-adjacent photodiodes may be summed at the shared floating diffusion node and read out as a summed signal or may be individually transferred to the shared floating diffusion node and read out individually.

Abstract: A backside illuminated image sensor with an array of pixels formed in a substrate is provided. To improve surface planarity, bond pads formed at the periphery of the array of pixels may be recessed into a back surface of the substrate. The bond pads may be recessed into a semiconductor layer of the substrate, may be recessed into a window in the semiconductor layer, or may be recessed in a passivation layer and covered with non-conductive material such as resin. In order to further improve surface planarity, a window may be formed in the semiconductor layer at the periphery of the array of pixels, or scribe region, over alignment structures. By providing an image sensor with improved surface planarity, device yield and time-to-market may be improved, and window framing defects and microlens/color filter non-uniformity may be reduced.