Abstract: An apparatus and method of forming a heat exchanger includes forming a monolithic core body having a first set of flow passages and a core coefficient of thermal expansion, and additively manufacturing onto the monolithic core a first manifold defining a first fluid inlet for the first set of flow passages.

Abstract: A computing system obtains image data representing images. Each of the images is captured at different time points of a physical environment. The physical environment comprises a first object and a second object. The computing system executes a control system to augment the physical environment. The control system detects a group forming in the images. The control system tracks an aspect of a movement, of a given object, in the group. The control system simulates the physical environment and the movement, of the given object, in the group in a simulated environment. The control system evaluates simulated actions in the simulated environment for a predefined objective for the physical environment. The predefined objective is related to an interaction between objects in the group. The control system generates based on evaluated simulated actions and autonomously from involvement by any user of the control system, an indication to augment the physical environment.

Abstract: A computing system responsive to obtaining original image data, detects a set of data point(s), in the original image data, that indicates an object. The system determines, based on the set of data point(s), a set of pixels associated with the object in the original image data. The system generates an alternative visual identifier for the object that provides a unique identifier for the set of pixels absent in the original image data. The system generates, autonomously from intervention by any user of the computing system, pixel information to conceal feature(s) of the object. The system obtains modified image data comprising the alternative visual identifier. The modified image data further comprises the feature(s) of the object in the original image data visually concealed in the modified image data according to the pixel information. The system outputs an image representation of a trajectory of the object through the modified image data.

Abstract: A computing system receives historical data. The historical data comprises physical actions taken in an experiment in a physical environment. The experiment comprises user-defined stages. The historical data comprises a recorded outcome, according to user-defined performance indicator(s) related to the user-defined stages, for each physical action taken in the experiment. The system generates, by a discrete event simulator, a computing representation of a simulated environment of the physical environment. The simulated environment comprises processing stages. The system obtains simulation data. The simulation data comprises simulated actions taken by the discrete event simulator. The simulation data comprises a predicted outcome, according to user-defined performance indicator(s) related to the processing stages, for each simulated action taken by the discrete event simulator. The system validates accuracy of the discrete event simulator at predicting the recorded outcome in the experiment.

Abstract: A computing system receives historical data. The historical data comprises physical actions taken in an experiment in a physical environment. The experiment comprises user-defined stages. The historical data comprises a recorded outcome, according to user-defined performance indicator(s) related to the user-defined stages, for each physical action taken in the experiment. The system generates, by a discrete event simulator, a computing representation of a simulated environment of the physical environment. The simulated environment comprises processing stages. The system obtains simulation data. The simulation data comprises simulated actions taken by the discrete event simulator. The simulation data comprises a predicted outcome, according to user-defined performance indicator(s) related to the processing stages, for each simulated action taken by the discrete event simulator. The system validates accuracy of the discrete event simulator at predicting the recorded outcome in the experiment.

Abstract: A computing system responsive to obtaining original image data, detects a set of data point(s), in the original image data, that indicates an object. The system determines, based on the set of data point(s), a set of pixels associated with the object in the original image data. The system generates an alternative visual identifier for the object that provides a unique identifier for the set of pixels absent in the original image data. The system generates, autonomously from intervention by any user of the computing system, pixel information to conceal feature(s) of the object. The system obtains modified image data comprising the alternative visual identifier. The modified image data further comprises the feature(s) of the object in the original image data visually concealed in the modified image data according to the pixel information. The system outputs an image representation of a trajectory of the object through the modified image data.

Abstract: A computing system obtains image data representing images. Each of the images is captured at different time points of a physical environment. The physical environment comprises a first object and a second object. The computing system executes a control system to augment the physical environment. The control system detects a group forming in the images. The control system tracks an aspect of a movement, of a given object, in the group. The control system simulates the physical environment and the movement, of the given object, in the group in a simulated environment. The control system evaluates simulated actions in the simulated environment for a predefined objective for the physical environment. The predefined objective is related to an interaction between objects in the group. The control system generates based on evaluated simulated actions and autonomously from involvement by any user of the control system, an indication to augment the physical environment.

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

Abstract: Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The structure includes: a transistor formed over a semiconductor material and an underlying substrate; and multiple isolated contact regions under a body or channel of the transistor, structured to provide a local potential to the body of the transistor at different locations.

Abstract: Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

Abstract: Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region.

Abstract: Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract: A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.

Abstract: A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.

Abstract: Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.