Abstract: A fingerprint sensor with programmable sensing patterns is disclosed in one embodiment of the invention as including a fingerprint sensing circuit having multiple I/O interconnects. The I/O interconnects are configured to sequentially drive a plurality of fingerprint sensing elements. A memory device may be operably coupled to the fingerprint sensing circuit. A programmable data structure, such as a table, file, character string, numeric value, array, or the like may be stored in the memory device to designate a pattern for driving the fingerprint sensing elements. The fingerprint sensing circuit is configured to drive the fingerprint sensing elements according to the designated pattern. In selected embodiments, the fingerprint sensing elements may include transmitting elements, receiving elements, or a combination thereof.

Abstract: An apparatus and method for detecting the presence of a finger on a fingerprint sensor is disclosed in one embodiment of the invention as including transmitting a probing signal, comprising a series of probing pulses, to a fingerprint sensing area. A response signal, comprising a series of response pulses, is received from the fingerprint sensing area in response to the probing signal. An upper reference signal is generated and finger activity is detected on the fingerprint sensing area by monitoring whether the peaks of the response pulses exceed the reference signal.

Abstract: An apparatus for reducing power consumption in fingerprint-sensing circuits is disclosed in one embodiment of the invention as including a fingerprint sensing area onto which a user can apply a fingerprint. An integrated circuit communicates with the fingerprint sensing area and is configured to detect finger activity over the fingerprint sensing area. The integrated circuit includes a primary logic portion configured to assume control of the integrated circuit when finger activity is detected over the fingerprint sensing area. The integrated circuit also includes a secondary logic portion configured to assume control of the integrated circuit and shut off power to the primary logic portion when finger activity is not detected over the fingerprint sensing area.

Abstract: An apparatus for culling substantially redundant data in a fingerprint sensing circuit is disclosed in one embodiment of the invention as including an input module, a storage module, a comparator module, and a determination module. The input module may receive sets of data samples from an array of fingerprint sensing elements. The sets of data samples may be stored by the storage module. The comparator module may calculate a difference between each data sample from a first-received set, and a corresponding data sample from a second-received set. The determination module may count the number of difference values that exceed a predetermined difference limit, and identify the second set of data samples as redundant if the number of difference values counted is less than a pre-set count limit.

Abstract: A system and method is disclosed for minimizing power consumption of a sensor unit that is capable of detecting an object. Main circuitry operates the sensor unit in a high power mode of operation when the sensor unit detects an object. Low power control circuitry operates the sensor unit in a low power mode of operation when the sensor unit does not detect an object within a pre-determined period of time. The low power control circuitry also comprises a counter to periodically determine when to restore the sensor unit to a high power mode of operation. One advantageous embodiment of the sensor unit is a fingerprint sensor unit for detecting a finger to obtain fingerprint information.

Abstract: An apparatus for reducing noise in fingerprint sensing circuits is disclosed in one embodiment of the invention as including a fingerprint sensing area onto which a user can apply a fingerprint. An analog front end is coupled to the fingerprint sensing area and is configured to generate an analog response signal. An analog-to-digital converter (ADC) samples the analog response signal and converts the sample to a digital value, which may be received by a digital device such as a processor or CPU. To reduce the amount of the noise that is present in the analog response signal and therefore reflected in the digital value, the digital device may be shut down while the ADC is sampling the analog response signal.

Abstract: A fingerprint sensing circuit for reducing noise and parasitic capacitive coupling is disclosed in one embodiment of the invention as including a plurality of transmitting elements to sequentially emit a probing signal. A digital ground is provided to ground digital components in the fingerprint sensing circuit. A quiet ground, separate from and quieter than the digital ground, is provided to ground transmitting elements that are not transmitting the probing signal. Similarly, control logic is provided to connect, to the quiet ground, transmitting elements that are not transmitting the probing signal, while disconnecting, from the quiet ground, transmitting elements that are emitting the probing signal. The quiet ground helps to reduce the adverse effects of parasitic capacitive coupling and noise on the inactive transmitting elements.

Abstract: A fingerprint sensor with programmable sensing patterns is disclosed in one embodiment of the invention as including a fingerprint sensing circuit having multiple I/O interconnects. The I/O interconnects are configured to sequentially drive a plurality of fingerprint sensing elements. A memory device may be operably coupled to the fingerprint sensing circuit. A programmable data structure, such as a table, file, character string, numeric value, array, or the like may be stored in the memory device to designate a pattern for driving the fingerprint sensing elements. The fingerprint sensing circuit is configured to drive the fingerprint sensing elements according to the designated pattern. In selected embodiments, the fingerprint sensing elements may include transmitting elements, receiving elements, or a combination thereof.

Abstract: A fingerprint sensor in accordance with the invention includes a non-conductive substrate providing a first surface onto which a user can apply a fingerprint to be sensed. A sensor circuit is applied to a second surface of the non-conductive substrate opposite the first surface to sense a fingerprint when juxtaposed proximally thereto. An electrostatic discharge conductor is applied to the non-conductive surface and is located between an area where a fingerprint is swiped and the sensor circuit. The electrostatic discharge conductor discharges electrostatic charge resulting from a user swiping a fingerprint across the first surface.

Abstract: A method and circuit capable of handling skew between a clock and data signal up to +/? one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

Abstract: A false DE rejection system is described. DEs are ignored during a programmable vertical lockout period. Internal timing is used during the vertical lockout period to count the number of vertical lines to ignore. The first DE received after the vertical lockout period signifies the start of the next graphics frame. Default video is output during the vertical lockout period. The TCON is synchronized to the start of the graphics frame. A horizontal line length timer measures the timing for the horizontal line length. The horizontal line length timer may also keep a moving average of all of the lines that it has measured. This helps to ensure that the TCON does not get out-of-sync with the input stream during the vertical blanking periods. The DE rejection system includes automatic blanking detection that ignores DEs that occur after the end of a predetermined graphics frame. The vertical lockout does not occur until there has been no DE for an entire line.

Abstract: The present invention is related to staggering data to reduce noise in a graphics display system. Line-to-line data staggering is achieved by staggering the starting point at which data is transmitted within each line of data. Frame-to-frame staggering is implemented by staggering the starting point of the first line of data from its value in the previous frame by a predetermined value each frame. Alternatively, frame-to-frame data staggering can be performed every other frame instead of every frame.

Abstract: A column driver for a graphics display has reduced power consumption by sharing power between upper and lower column amplifiers. The upper column amplifier operates over an upper supply range, while the lower column amplifier operates over a lower supply range. The upper and lower amplifiers have the substantially the same quiescent operating current such that the total operating current for the column drivers in the graphics display is reduced by a factor of two. Each column amplifier can be driven over half of the power-supply range such that lower voltage amplifiers may be employed for the column driver amplifiers.

Abstract: The present invention provides a point-to-point data bus architecture and a protocol for a graphics system. The TCON transmits the data to the column drivers using separate point-to-point data buses. Data may be transmitted to the column drivers during a horizontal blanking period resulting in more data being written to the column drivers as compared to a typical graphical display system. As each point-to-point data bus contains only the data for its corresponding column driver the instantaneous data rate to any column driver is lower than in conventional multi-drop architectures. The point-to-point system has fewer printed circuit board (PCB) lines and a lower loop area than a conventional multi-drop system. A protocol may also be implemented. The protocol may provide for system level control and coordination of column drivers and other display system components. This protocol allows the TCON to control the operation of the column drivers without the need for extra PCB lines.

Abstract: An improved memory for graphics displays includes an improved memory cell. Data may be written and read from the single bit cell simultaneously, eliminating the need for additional memory circuits to service an N column driver for a display. Additionally, the architecture of the memory allows for a signal input port for writing the data to the cell while allowing for multiple parallel output ports for reading the data. The unique architecture eliminates the need for addressing logic and refresh circuitry for display applications.

Abstract: A data/clock deskewing methodology uses a delay-locked loop (DLL) circuit. The DLL circuit generates a number of clock phases in response to an input clock, where each clock phase is delayed relative to the input clock signal. The clock phases are used to sample data from a data line. The sampled data is checked against a preamble pattern (a sequence of known data). A digital deskew control block selects one of the clock phases after analyzing the results of preamble pattern check such that subsequently received data is sampled with the appropriately selected clock phase.

Abstract: A differential amplifier circuit receives full range differential input signals, and produces a full range output signal, using CMOS transistors designed for one-half such operating voltage. The positive and negative input signals differentially drive first and second CMOS transistors. The source terminals of such first and second CMOS transistors are coupled to a current steering circuit by a pair of lower protection transistors; the gate terminals of such lower protection transistors are driven by level-shifted counterparts of the positive and negative input signals. The drain terminals of the first and second CMOS transistors are coupled to a common node via a pair of upper protection transistors, the gate terminals of which are also driven by the level-shifted counterparts of the input signals.

Abstract: A differential amplifier circuit receives full range differential input signals, and produces a full range output signal, using CMOS transistors designed for one-half such operating voltage. The positive and negative input signals differentially drive first and second CMOS transistors. The source terminals of such first and second CMOS transistors are coupled to a current steering circuit by a pair of lower protection transistors; the gate terminals of such lower protection transistors are driven by level-shifted counterparts of the positive and negative input signals. The drain terminals of the first and second CMOS transistors are coupled to a common node via a pair of upper protection transistors, the gate terminals of which are also driven by the level-shifted counterparts of the input signals.

Abstract: A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.

Abstract: A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.