Patents by Inventor Richard Cliff

Richard Cliff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180308614
    Abstract: Design and construction is described for remotely-controllable variable MRI-compatible low-noise inductors and capacitors, each having a wide variation range and each occupying a volume of no more than 30 cubic centimeters. To optimize noise figure in 3-tesla medical MRI antenna arrays, an exemplar capacitor is connected in series following an antenna element and an exemplar inductor is connected in shunt following an exemplar capacitor. Exemplar Inductors are constructed as a pair of flux-coupled coils which are connected by a movable or rotatable contactor positioned by folded and nested stepping mechanisms. Exemplar inductors are constructed from two flux-coupled parallel solenoid coils or from two flux-coupled toroid-segment coils. Exemplar capacitors are designed and constructed in an analogous manner. Other miniature inductor and capacitor embodiments are possible. Miniature variable resistor embodiments can be constructed in a manner analogous to that of the capacitors.
    Type: Application
    Filed: June 24, 2018
    Publication date: October 25, 2018
    Inventor: Richard Cliff
  • Publication number: 20180028691
    Abstract: Described are methods for the detection, in the eye of an individual, of protein aggregates or other misfolded proteins associated with disease using peptide or peptide mimic probes that preferentially associate with the protein aggregates or misfolded proteins, which can be accomplished non-invasively.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 1, 2018
    Applicant: SYSTEM OF SYSTEMS ANALYTICS, INC.
    Inventors: Giora FEUERSTEIN, Richard Cliff
  • Patent number: 9795692
    Abstract: Described are methods for the detection, in the eye of an individual, of protein aggregates or other misfolded proteins associated with disease using peptide or peptide mimic probes that preferentially associate with the protein aggregates or misfolded proteins, which can be accomplished non-invasively.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 24, 2017
    Assignee: SYSTEM OF SYSTEMS ANALYTICS, INC.
    Inventors: Giora Feuerstein, Richard Cliff
  • Publication number: 20150125396
    Abstract: Described are methods for the detection, in the eye of an individual, of protein aggregates or other misfolded proteins associated with disease using peptide or peptide mimic probes that preferentially associate with the protein aggregates or misfolded proteins, which can be accomplished non-invasively.
    Type: Application
    Filed: June 5, 2014
    Publication date: May 7, 2015
    Applicant: Adlyfe, Inc.
    Inventors: Giora Feuerstein, Richard Cliff
  • Publication number: 20140354389
    Abstract: A new family of programmable low-noise RF impedance transformers has been developed. These new transformers can be configured and operated to compensate for variable antenna output impedance. This enables better optimization of RF receiving-system SNR. For some applications, these new devices can be more compact and less expensive than any previously available. In particular, such new transformers can improve MRI system performance. This requires additional new art because MRI systems demand components which are not ferromagnetic, which do not produce spurious MR signals and which add very little noise to received RF signals. In various embodiments, these new transformers are comprised of remotely-controlled variable capacitors and inductors which are connected in networks between antenna element outputs and their following LNA inputs. These new step-programmable inductors and capacitors can be either electrically or pneumatically actuated.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventor: Richard Cliff
  • Patent number: 8407649
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 26, 2013
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Christopher Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Publication number: 20120217998
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Applicant: ALTERA CORPORATION
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Christopher Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Patent number: 8201129
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: June 12, 2012
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Publication number: 20090224800
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Application
    Filed: May 13, 2009
    Publication date: September 10, 2009
    Applicant: ALTERA CORPORATION
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Patent number: 7584447
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: September 1, 2009
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Publication number: 20070200596
    Abstract: A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.
    Type: Application
    Filed: February 24, 2006
    Publication date: August 30, 2007
    Inventors: Andy Lee, Christopher Lane, Ketan Zaveri, Richard Cliff, Cameron McClintock, Srinivas Reddy, David Lewis
  • Patent number: 7164903
    Abstract: An integrated N-way Wilkinson power divider is described. In one embodiment, the N-way Wilkinson power divider uses a conductor layer with a cross-over (or cross-under) resistor insulated from the conducting layer by an insulating bridge. In one embodiment, the width of the transmission line underneath a cross-over resistor is adjusted to improve performance In one embodiment, a three-way Wilkinson power divider is formed using microstrip transmission lines on a single-layer substrate that supports the microstrip transmission lines, dielectric insulators, and resistors.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: January 16, 2007
    Assignee: Smiths Interconnect Microwave Components, Inc.
    Inventors: Richard Cliff, Michael J. Kettner, Robert J. Wright, Andrew J. Kettner, Patrick A. Biebersmith, Juan G. Ayala
  • Publication number: 20070011578
    Abstract: A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.
    Type: Application
    Filed: April 19, 2006
    Publication date: January 11, 2007
    Applicant: Altera Corporation
    Inventors: David Lewis, Robert Blake, Richard Cliff, Srinivas Reddy
  • Publication number: 20070008000
    Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
    Type: Application
    Filed: August 1, 2006
    Publication date: January 11, 2007
    Inventors: Andy Lee, Wanli Chang, Cameron McClintock, John Turner, Brian Johnson, Chiao Hwang, Richard Chang, Richard Cliff
  • Patent number: 7161381
    Abstract: A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: January 9, 2007
    Assignee: Altera Corporation
    Inventors: Srinivas Reddy, David Jefferson, Christopher F. Lane, Vikram Santurkar, Richard Cliff
  • Patent number: 7058920
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: June 6, 2006
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Timothy Betz, David Lewis
  • Publication number: 20060033527
    Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
    Type: Application
    Filed: August 12, 2005
    Publication date: February 16, 2006
    Inventors: Andy Lee, Cameron McClintock, Brian Johnson, Richard Cliff, Srinivas Reddy, Chris Lane, Paul Leventis, Vaughn Betz, David Lewis
  • Patent number: 6970014
    Abstract: An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: November 29, 2005
    Assignee: Altera Corporation
    Inventors: David M. Lewis, Paul Leventis, Andy L. Lee, Brian D. Johnson, Richard Cliff, Srinivas T. Reddy, Christopher F. Lane, Cameron R. McClintock, Vaughn Betz, Chris Wysocki, Alexander R. Marquardt
  • Publication number: 20050151564
    Abstract: Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.
    Type: Application
    Filed: December 3, 2004
    Publication date: July 14, 2005
    Applicant: Altera Corporation
    Inventors: Cameron McClintock, Richard Cliff, Bonnie Wang
  • Patent number: 6895570
    Abstract: An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire. A routing architecture is an array that includes rows and columns of function blocks.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: May 17, 2005
    Assignee: Altera Corporation
    Inventors: David M. Lewis, Vaughn Betz, Paul Leventis, Michael Chan, Cameron R. McClintock, Andy L. Lee, Christopher F. Lane, Srinivas T. Reddy, Richard Cliff