Patents by Inventor Richard E. Schenker

Richard E. Schenker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210091194
    Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Rami HOURANI, Richard VREELAND, Giselle ELBAZ, Manish CHANDHOK, Richard E. SCHENKER, Gurpreet SINGH, Florian GSTREIN, Nafees KABIR, Tristan A. TRONIC, Eungnak HAN
  • Publication number: 20210090990
    Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Rami HOURANI, Manish CHANDHOK, Richard E. SCHENKER, Florian GSTREIN, Leonard P. GULER, Charles H. WALLACE, Paul A. NYHUS, Curtis WARD, Mohit K. HARAN, Reken PATEL
  • Publication number: 20210090997
    Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Mohit K. HARAN, Reken PATEL, Richard E. SCHENKER, Charles H. WALLACE
  • Publication number: 20210082800
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 18, 2021
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 10937689
    Abstract: In one embodiment, a trench may be formed in a dielectric surface, and the trenched may be lined with a liner. The trench may be filled with a metal, and the metal may be recessed below an opening of the trench. The liner may be converted into a dielectric, and a hard mask may be deposited into the trench.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Manish Chandhok, Satyarth Suri, Tristan A. Tronic, Christopher J. Jezewski, Richard E. Schenker
  • Publication number: 20210050261
    Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 18, 2021
    Inventors: Kevin LIN, Robert L. BRISTOL, Richard E. SCHENKER
  • Patent number: 10892223
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Publication number: 20210005511
    Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 7, 2021
    Inventors: Kevin LIN, Robert L. BRISTOL, Richard E. SCHENKER
  • Publication number: 20200411501
    Abstract: An integrated circuit structure includes an active region containing more active semiconductor devices, wherein the active region comprises a first grating of metal and dielectric materials with only vertically aligned structures thereon. A transition region containing inactive structures is adjacent to the active region, wherein the transition region comprises a second grating of metal and dielectric materials having at least one of vertical aligned structures and vertical random structures thereon. Both the active regions and the transition regions have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Gurpreet SINGH, Eungnak HAN, Paul A. NYHUS, Florian GSTREIN, Richard E. SCHENKER
  • Patent number: 10867853
    Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert L. Bristol, Richard E. Schenker
  • Publication number: 20200388534
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 10, 2020
    Inventors: Leonard P. GULER, Michael HARPER, Suzanne S. RICH, Charles H. WALLACE, Curtis WARD, Richard E. SCHENKER, Paul NYHUS, Mohit K. HARAN, Reken PATEL, Swaminathan SIVAKUMAR
  • Patent number: 10804141
    Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Robert L. Bristol, Richard E. Schenker
  • Publication number: 20200294998
    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: AARON D. LILAK, EHREN MANNEBACH, ANH PHAN, RICHARD E. SCHENKER, STEPHANIE A. BOJARSKI, WILLY RACHMADY, PATRICK R. MORROW, JEFFERY D. BIELEFELD, GILBERT DEWEY, HUI JAE YOO
  • Patent number: 10770291
    Abstract: Grating based plugs and cuts for feature end formation for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a hardmask layer above an interlayer dielectric (ILD) material layer. A first patterned hardmask layer is formed above the hardmask layer. A second patterned hardmask layer is formed above the first patterned hardmask layer. A lithographic patterning mask is formed above the second patterned hardmask layer. Portions of the second patterned hardmask layer not protected by the regions of the lithographic patterning mask are removed to form a third patterned hardmask layer and then the lithographic patterning mask is removed. A combined pattern of the third patterned hardmask layer and the first patterned hardmask layer is transferred to the hardmask layer and to the ILD material layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Charles H. Wallace
  • Publication number: 20200203212
    Abstract: A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Miriam R. RESHOTKO, Richard E. SCHENKER, Nafees KABIR
  • Publication number: 20200090987
    Abstract: Passivating silicide-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. Each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer. A metal silicide layer is on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the metal silicide layer and on the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of the metal silicide layer on one of the plurality of conductive lines.
    Type: Application
    Filed: June 20, 2017
    Publication date: March 19, 2020
    Inventors: Manish CHANDHOK, Sudipto NASKAR, Richard E. SCHENKER
  • Publication number: 20200075334
    Abstract: An integrated circuit die including tight pitch features and a method of fabricating an integrated circuit die using subtractive patterning by asymmetric spacer formation is disclosed. The integrated circuit die a substrate and a first multitude of features above the substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.
    Type: Application
    Filed: March 31, 2017
    Publication date: March 5, 2020
    Inventors: Richard E. SCHENKER, Robert B. TURKOT, Jr.
  • Publication number: 20200066521
    Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 27, 2020
    Inventors: Kevin LIN, Rami HOURANI, Elliot N. TAN, Manish CHANDHOK, Anant H. JAHAGIRDAR, Robert L. BRISTOL, Richard E. SCHENKER, Aaron Douglas LILAK
  • Publication number: 20200066629
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Application
    Filed: December 23, 2016
    Publication date: February 27, 2020
    Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN
  • Patent number: 10553532
    Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Manish Chandhok, Robert L. Bristol, Mauro J. Kobrinsky, Kevin Lin