Abstract: Methods and apparatuses are described for wireless communications coexistence. In one aspect, a first device may detect an interference produced by a second device co-located with the first device. The first device may communicate with an access point (AP) using a free or open band and the second device may communicate with a cellular network (e.g., LTE network). In response to the detected interference, a message may be transmitted to the AP from the first device with information for the AP to determine whether to switch to a different channel in the open band to communicate with the first device. The AP may receive such a message from each terminal in at least a subset of associated terminals. The AP may determine, from the messages received, to switch to the different channel in the open band and may transmit a message to the associated terminals indicating the switch.

Abstract: Methods and apparatuses are described for wireless communications coexistence. In one aspect, a first device may detect an interference produced by a second device co-located with the first device. The first device may communicate with an access point (AP) using a free or open band and the second device may communicate with a cellular network (e.g., LTE network). In response to the detected interference, a message may be transmitted to the AP from the first device with information for the AP to determine whether to switch to a different channel in the open band to communicate with the first device. The AP may receive such a message from each terminal in at least a subset of associated terminals. The AP may determine, from the messages received, to switch to the different channel in the open band and may transmit a message to the associated terminals indicating the switch.

Abstract: A dynamic random access memory (DRAM) single in-line memory module (SIMM) having optimized physical dimensions achieves high speed and high storage capacity. The DRAM SIMM has a printed circuit board with a multi-contact connector, a plurality of DRAM sets, each set having a plurality of DRAM chips mounted on the printed circuit board, and a plurality of buffers which are also mounted on the printed circuit board. The number of buffers is equal to the number of DRAM sets. Various standard DRAM chips can be used on the SIMM to achieve different performance and storage capacity, while maintaining plug compatibility of the multi-contact connector with a memory board. The buffers buffer the control and address signals for the DRAM chips, which is necessary to keep control and address signal integrity due to the number of DRAMS. The buffers permit each DRAM to receive the necessary control and address signals in a more synchronized fashion, so that relative delays are well controlled.

Abstract: A method and apparatus for selectively invalidating tag data related to data stored in high speed processor cache memory systems. The tag data to be invalidated, due to processor operations and cache memory misses, is stored in two tag stores and indicia related to the tag data to be invalidated is stored in a purge queue. Further improvement in system performance is provided by selective tag data and indicia elimination.

Abstract: A method for preserving data transfer order in a pipeline computer system, wherein a first block of data is transferred from a first device to at least a second device during a first computer cycle. Simultaneously, the first block of data is stored within the first device. Druing a second computer cycle, a second block of data is transferred from the first device to the second device, and an acknowledge signal is issued, indicating the success or failure of the transfer of the first block of data. If the acknowledge signal indicates a failed data transfer, a reject signal is issued and data transfer is restarted beginning with the previously failed data transaction which has been stored within the first device, and data transfer then continues with a preserved data transfer order.

Abstract: A computer system having a plurality of processors sharing common memory and data bus structures and operable to perform atomic operations which comprise several instruction actions, wherein the processor performing the atomic operation prevents memory access interruptions by other processors by locking out other processors during the atomic operation. The system bus includes signal paths accommodating bus lock request and bus lock signals which are provided and received by each processor, which signals are initiated by specific bus lock and lock release instructions added to each processor instruction set.

Abstract: A method and apparatus for granting, to a select processor in a multiprocessor computing system, exclusive access to a bus for issuance of address, data and command signals thereover, wherein each processor includes bus lock request and bus lock assert elements which provide corresponding bus request and bus hold signals which are recognized by corresponding elements included in other processors connected to the bus. The bus lock according to the present invention assures the processor having lock status of privacy on the bus necessary to complete a specified operation without interruption from the other processors.

Abstract: Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction words are powers of 2 in length, (measured in terms of the smallest machine addressable unit) typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2. To provide maximum operating efficiency, each functional (or processing) unit executes a component of an instruction word during an execution cycle. The type and length of the instruction word are indicated by one of the bit fields of the instruction word, which permits the apparatus to properly detect, store and transfer the instruction word to the appropriate functional unit.

Abstract: A decentralized, pipelined, synchronous bus arbitration scheme which allows almost completely fair arbitration between multiple devices competing for the use of a communication bus while allowing the device that last used the bus faster access to the bus if no other device is competing for its use. The arbitration method and apparatus according to the present invention allows all competing devices equal access to the bus, with the exception that when bus requests are posted simultaneously, the device with the higher priority will always be granted use of the bus first.

Abstract: A bit selection and routing apparatus and method selects m data signals from among its n available data inputs and groups those m signals on its output lines. The apparatus employs a two-dimensional array of signal selection elements which are multiplexing elements. The circuitry is implemented in NMOS technology using pass transistors. The apparatus can be placed in a data flow path and can pass data either unaltered, in a selection mode, in a shift mode, and in a partial data pass mode wherein an upper portion of the input word is set to a predetermined value. The selection elements are connected to route the selected input signals to selected output lines in a predetermined order.

Abstract: A system for transferring solicited message packets between data processors coupled on a serial communications path. A solicitor processor allocates a portion of its memory for storage of solicited message packets which might be solicited and received from at least one other data processor. The solicitor data processor defines a sequence of operations to be performed on any such received solicited message packets at that processor. The solicitor processor also transfers a solicited message parameter signal to the solicitee data processor where that signal is representative of a predetermined header portion for solicited data packets which might be generated by the solicitee data processor and transferred to the solicitor data processor. The header portion of a solicited message packet relates one or more of the sequences of operations which are to be associated with that packet.

Abstract: A ring communications network which is automatically reconfigured based on the detection of system defects.

Abstract: A ring communications system having a double ring format where the integrity of both rings is continuously checked, and where repair of the network is automatically accomplished upon the detection of the return to operation of a defective ring.

Abstract: A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is coupled in series along the ring. Each terminal is adapted to transmit (at an associated data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. The received digital signal is applied to a phase locked loop characterized by a hold time which exceeds its lock time. The phase locked loop extracts a local timing signal for re-clocking the received digital signal. The transmission time of N bits is less than the hold time of the phase locked loop. Each terminal monitors the re-clocked signal to identify when same valued consecutive bits are received for a period less than the phase locked loop hold time, and upon such detection to cause that terminal to generate at least one transition.

Abstract: A communications network including a plurality of terminals coupled together to provide a unidirectional communications ring. Each of the terminals is adapted to transmit (at an associated fixed data rate) a digital signal to the next downstream terminal on the ring. Each terminal is adapted to receive a digital signal at the data rate associated with the next upstream terminal. In each local terminal, there is a detector for detecting the received synchronization packets and associated data packets are generated for transmission to the next downstream terminal on the ring at a predetermined fixed data rate associated with the local terminal. The data of each transmitted data packet matches bit for bit the data of the corresponding received data packet.

Abstract: A token-passing, ring-based data communications network provides a distributive method and apparatus for detecting and regenerating a lost token. The method includes, after detection of the loss of the token, transmitting at a detecting node a data packet not including a token, the data packet uniquely identifying the transmitting node as the data source. Simultaneously, the transmitting node, after transmitting the tokenless data packet, strips all incoming data from the network. If the transmitted packet is successfully received by the transmitting node, a new token is generated by the node. If the packet is not received, the node defers to an arbitration method which includes delaying a next data packet transmission for a probabilistically determined period of time. The mean time upon which the probabilistic approach is based increases with each unsuccessful data packet transmission attempt.