Abstract: A scalar/vector processor capable of concurrent scaler and vector operations includes scalar resources to process scalar instructions, and vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions. The scalar resources include scalar registers, and the vector resources include vector registers. Decoding means decodes each of a number of address fields. Each field represents a register address to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below a selected moveable address value within a range of addresses encompassed by the address field.

Abstract: An improved high performance hardwired supercomputer data processing apparatus includes instruction means adpated to issue one and two parcel instructions. Instruction fetch means provides an instruction stream of two parcel items in sequence. Instruction decode means is responsive to each two parcel item for determining in one clock cycle whether the two parcel item is a single two parcel instruction or two one parcel instructions, for issuing each two parcel instruction for execution during the one clock cycle, and for issuing one then the other of the two one parcel instructions for execution in sequence during the one clock cycle and the next succeeding clock cycle.

Abstract: A delayed branch mechanism maintains the flow of an instruction pipeline in a scalar/vector processor having an instruction cache and including instruction fetch means, a program counter, and instruction decode/issue means coupled to the instruction cache by means of the instruction pipeline. Conditional branch instructions are rated as likely conditional branch instructions or unlikely conditional branch instructions based on a probability that their branch conditions will be met. A number of pipeline clock periods required for testing the branch conditions are determined. The likely conditional branch instructions are issued and executed including transferring a branch-to-address to the program counter during the number of pipeline clock periods irrespective of a successful meeting of the branch conditions. A number of useful instructions sufficient to issue within the number of pipeline clock periods are placed into the instruction stream following the likely conditional branch instructions.

Abstract: A rack-mount data server includes a housing, a plurality of data server components supported by the housing, the components including at least one peripheral storage device, a logic chassis for the data server, at least one disk drive on which the data server stores files, and at least one power supply, and a plurality of racks coupled with the housing to accommodate the data server components, the racks including a first topmost rack accommodating the at least one peripheral storage device and a second rack accommodating the logic chassis, the housing supporting the second rack underneath the first rack as the second topmost rack. The data server also includes a front door and a top door, the top door and the front door being interlockable with each other such that when the top door and the front door are in their closed positions, one of the top door and the front door locks the other of the top door and the front door in its closed position.

Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.

Abstract: A vector processing system includes a main memory, vector registers, vector resources for accessing memory to transfer vector data between main memory and the vector registers and to perform operations on the vector data. Data words stored in non-consecutive address locations of a segment of main memory are accessed for processing. Offset address values of a number of the data words are stored in consecutive elements of a first vector register. A vector gather instruction is executed which adds each offset address value to a base address value to calculate main memory addresses representing main memory storage locations of the data words, retrieves the data words from the main memory, and stores the data words in consecutive elements of a second vector register in an order corresponding to that in which the offset address values are stored in the first vector register.

Abstract: A sequence of conditional vector IF statements is processed by employing a mask register and a condition register. Each conditional vector IF statement is typically performed on two vector registers, each having vector elements. A first conditional vector IF statement in the sequence is processed for those vector elements corresponding to set bits in the mask register. Bits are set in the condition register to reflect those vector elements which correspond to the set bits in the mask register for which the conditional vector IF statement is satisfied. The contents of the condition register are then moved into the mask register. A next conditional vector IF statement in the sequence is then processed for those vector elements corresponding to the new set bits in the mask register. Bits are then set in the condition register to reflect those vector elements which correspond to the new set bits in the mask register for which the conditional vector IF statement is satisfied.

Abstract: A vector processor includes functional unit paths, each having an input and an output, and with at least one functional unit path including a plurality of pipelined functional elements coupled to the respective path input and output in parallel. The functional elements have different pipeline lengths to complete processing of operands applied to the path input. Program instruction initiation means responds to a first instruction to initiate processing of first operand data in a first of the functional elements, and responds to a second instruction to initiate the processing of second operand data in a second of the functional elements dependent upon completion of the first instruction but only if the second functional element has a pipeline length equal to or greater than the pipeline length of the first functional element.

Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.

Abstract: The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.