Abstract: To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.

Abstract: To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.

Abstract: A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGA in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising thecoprocessor and processor are provided as well.

Abstract: A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.

Abstract: In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.

Abstract: A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration gives priority BMs with a GBF greater than zero in a stratified protocol where requesting BMs with the same highest priority are granted access first. The GBF of a BM is decremented each time an access is granted. Requesting BMs with a GBF equal to zero are fairly arbitrated when there are no requesting BMs with GBFs greater than zero wherein they receive equal access using a frozen arbiter status. The bus access time may be partitioned into bus intervals (BIs) each comprising N clock cycles. BIs and GBFs may be modified to guarantee balanced access over multiple BIs in response to error conditions or interrupts.

Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.

Abstract: A method and system for reducing latency of a snoop tenure. A bus macro may receive a snoopable transfer request. The bus macro may determine which snoop controllers in a system will participate in the snoop transaction. The bus macro may then identify which participating snoop controllers are passive. Passive snoop controllers are snoop controllers associated with cache memories with cache lines only in the shared or invalid states of the MESI protocol. The snoop request may then be completed by the bus macro without waiting to receive responses from the passive participating snoop controllers. By not waiting for responses from passive snoop controllers, the bus macro may be able to complete the snoop request in a shorter amount of time thereby reducing the latency of the snoop tenure and improving performance of the system bus.

Abstract: A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

Abstract: A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

Abstract: A method and system for reducing latency of a snoop tenure A bus macro may receive a snoopable transfer request. The bus macro may determine which snoop controllers in a system will participate in the snoop transaction. The bus macro may then identify which participating snoop controllers are passive. Passive snoop controllers are snoop controllers associated with cache memories with cache lines only in the shared or invalid states of the MESI protocol. The snoop request may then be completed by the bus macro without waiting to receive responses from the passive participating snoop controllers. By not waiting for responses from passive snoop controllers, the bus macro may be able to complete the snoop request in a shorter amount of time thereby reducing the latency of the snoop tenure and improving performance of the system bus.

Abstract: A method, computer system and set of signals are disclosed allowing for communication of a data transfer, via a bus, between a master and a slave using a single transfer request regardless of transfer size and alignment. The invention provides three transfer qualifier signals including: a first signal including a starting byte address of the data transfer; a second signal including a size of the data transfer in data beats; and a third signal including a byte enable for each byte required during a last data beat of the data transfer. The invention is usable with single or multiple beat, aligned or unaligned data transfers. Usage of the three transfer qualifier signals provides the slave with how many data beats it will transfer at the start of the transfer, and the alignment of both the starting and ending data beats. As a result, the slave need not calculate the number of bytes it will transfer.

Abstract: A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration gives priority BMs with a GBF greater than zero in a stratified protocol where requesting BMs with the same highest priority are granted access first. The GBF of a BM is decremented each time an access is granted. Requesting BMs with a GBF equal to zero are fairly arbitrated when there are no requesting BMs with GBFs greater than zero wherein they receive equal access using a frozen arbiter status. The bus access time may be partitioned into bus intervals (BIs) each comprising N clock cycles. BIs and GBFs may be modified to guarantee balanced access over multiple BIs in response to error conditions or interrupts.

Abstract: In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro.

Abstract: A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer. The DMA has registers for storing base addresses and registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A power management device is coupled to the DMA control circuit and has logic for causing the computer system to enter a suspend mode. A base address register read circuit is coupled to the base address registers. Prior to entering the suspend mode, the base address register read circuit provides one of the base addresses to be read by a central processing unit (CPU) onto disk storage.