Patents by Inventor Richard H. Lane
Richard H. Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150187767Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. Semiconductor structures formed by these methods are also disclosed.Type: ApplicationFiled: March 16, 2015Publication date: July 2, 2015Inventors: Paul Grisham, Werner Juengling, Richard H. Lane
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Patent number: 8987834Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. Semiconductor structures formed by these methods are also disclosed.Type: GrantFiled: March 27, 2012Date of Patent: March 24, 2015Assignee: Micron Technology, Inc.Inventors: Paul Grisham, Richard H. Lane
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Publication number: 20120181605Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. Semiconductor structures formed by these methods are also disclosed.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Paul Grisham, Richard H. Lane
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Patent number: 8148775Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.Type: GrantFiled: February 4, 2010Date of Patent: April 3, 2012Assignee: Micron Technology, Inc.Inventors: Brent D. Gilgen, Paul Grisham, Werner Juengling, Richard H. Lane
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Patent number: 7943477Abstract: An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed.Type: GrantFiled: November 6, 2009Date of Patent: May 17, 2011Assignee: Round Rock Research, LLCInventor: Richard H. Lane
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Patent number: 7935602Abstract: The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.Type: GrantFiled: June 28, 2005Date of Patent: May 3, 2011Assignee: Micron Technology, Inc.Inventors: Hongmei Wang, Fred D. Fishburn, Janos Fucsko, T. Earl Allen, Richard H. Lane, Robert J. Hanson, Kevin R. Shea
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Publication number: 20100133609Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.Type: ApplicationFiled: February 4, 2010Publication date: June 3, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Brent D. Gilgen, Paul Grisham, Werner Juengling, Richard H. Lane
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Publication number: 20100055863Abstract: An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed.Type: ApplicationFiled: November 6, 2009Publication date: March 4, 2010Inventor: Richard H. Lane
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Patent number: 7629630Abstract: An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns is disclosed.Type: GrantFiled: November 21, 2001Date of Patent: December 8, 2009Assignee: Micron Technology, Inc.Inventor: Richard H. Lane
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Publication number: 20090294840Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase the effective gate length (“Leffective”) and the field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the Leffective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.Type: ApplicationFiled: June 2, 2008Publication date: December 3, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Brent D. Gilgen, Paul Grisham, Werner Juengling, Richard H. Lane
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Patent number: 7601598Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.Type: GrantFiled: October 1, 2007Date of Patent: October 13, 2009Assignee: Micron Technology, Inc.Inventors: Werner Juengling, Richard H. Lane
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Patent number: 7501672Abstract: A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which may be formed using one embodiment of the inventive method is also described.Type: GrantFiled: October 10, 2006Date of Patent: March 10, 2009Assignee: Micron Technology, Inc.Inventors: Fredrick D. Fishburn, Terrence B. McDaniel, Richard H. Lane
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Patent number: 7473644Abstract: Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of precise subresolution features useful for forming integrated circuits. The resulting symmetrical hardmask spacers with their symmetric upper portions may be used to accurately etch well-defined, high aspect ratio features in the underlying substrate. Some disclosed methods also enable simultaneous formation of hardmask structures of various dimensions, of both conventional and subresolution size, to enable etching structural features of different sizes in the underlying substrate.Type: GrantFiled: July 1, 2004Date of Patent: January 6, 2009Assignee: Micron Technology, Inc.Inventors: Richard H. Lane, Fred Fishburn
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Patent number: 7375014Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7348234Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: March 25, 2008Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7344977Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: March 18, 2008Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7329618Abstract: An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein received intermediate the pair of spaced features. While such spaced features are laterally pulled, a species is ion implanted into substrate material which is received lower than the pair of spaced features. After the ion implanting, the patterned photoresist layer is removed from the substrate. Other aspects and implementations are contemplated.Type: GrantFiled: June 28, 2005Date of Patent: February 12, 2008Assignee: Micron Technology, Inc.Inventors: Randall Culver, Terrence B. McDaniel, Hongmei Wang, James L. Dale, Richard H. Lane, Fred D. Fishburn
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Patent number: 7288817Abstract: The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer, a conducting layer, and a first insulating layer. Sidewall spacers are formed adjacent to the sides of the gate stack structure and a third insulating layer is formed over the gate stack and substrate. The third insulating layer and first insulating layer are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.Type: GrantFiled: January 12, 2005Date of Patent: October 30, 2007Assignee: Micron Technology, Inc.Inventors: Werner Juengling, Richard H. Lane
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Patent number: 7282131Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
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Patent number: 7273778Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.Type: GrantFiled: February 8, 2005Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein