Patents by Inventor Richard H. Livengood

Richard H. Livengood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7232526
    Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: June 19, 2007
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Gary Woods, Michael DiBattista
  • Patent number: 7205566
    Abstract: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in regions the semiconductor substrate.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: April 17, 2007
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Darren Slawecki
  • Patent number: 7183122
    Abstract: Nano-machining for circuit edits through the front side or backside of an integrated circuit may be performed using a scanning probe system. The system may create access holes with smaller dimensions and facilitate nano-machining endpoint detection in some embodiments.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Michael DiBattista, Richard H. Livengood, Elizabeth B. Varner, Randall C. White
  • Patent number: 7141439
    Abstract: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in region the semiconductor substrate.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: November 28, 2006
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Darren Slawecki
  • Publication number: 20040241999
    Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 2, 2004
    Applicant: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Gary Woods, Michael DiBattista
  • Patent number: 6825557
    Abstract: An integrated circuit device is disclosed. The device comprises a die that has functional units on a first surface and a cooling system arranged adjacent a second surface opposite the first surface. The cooling system comprises a least one microchannel to contain a cooling liquid and to allow flow of the cooling liquid and at least one reservoir arranged adjacent to a region of the die. There is at least one valve between the reservoir and the microchannel to allow the cooling liquid to flow into the reservoir wherein flow of the cooling liquid depends upon a temperature of the die region.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 30, 2004
    Assignee: Intel Corporation
    Inventors: Michael DiBattista, Richard H. Livengood
  • Patent number: 6780658
    Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Gary Woods, Michael DiBattista
  • Publication number: 20040113265
    Abstract: An integrated circuit device is disclosed. The device comprises a die that has functional units on a first surface and a cooling system arranged adjacent a second surface opposite the first surface. The cooling system comprises a least one microchannel to contain a cooling liquid and to allow flow of the cooling liquid and at least one reservoir arranged adjacent to a region of the die. There is at least one valve between the reservoir and the microchannel to allow the cooling liquid to flow into the reservoir wherein flow of the cooling liquid depends upon a temperature of the die region.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Applicant: Intel Corporation
    Inventors: Michael DiBattista, Richard H. Livengood
  • Publication number: 20030207578
    Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
    Type: Application
    Filed: June 5, 2003
    Publication date: November 6, 2003
    Applicant: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Gary Woods, Michael DiBattista
  • Patent number: 6579732
    Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: June 17, 2003
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Gary Woods, Michael DiBattista
  • Patent number: 6525922
    Abstract: A capacitor structure is formed on a substrate member having one or more via holes therein. Metallization portions within the via holes of the substrate member form part of the plates of the capacitor.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: February 25, 2003
    Assignee: Intel Corporation
    Inventors: Paul Winer, Richard H. Livengood, Suresh Ramalingam
  • Patent number: 6495454
    Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: December 17, 2002
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Valuri R. M. Rao
  • Patent number: 6448168
    Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: September 10, 2002
    Assignee: Intel Corporation
    Inventors: Valluri R. Rao, Jeffrey K. Greason, Richard H. Livengood
  • Publication number: 20020085336
    Abstract: A capacitor structure is formed on a substrate member having one or more via holes therein. Metallization portions within the via holes of the substrate member form part of the plates of the capacitor.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Paul Winer, Richard H. Livengood, Suresh Ramalingam
  • Publication number: 20020055272
    Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
    Type: Application
    Filed: December 20, 2001
    Publication date: May 9, 2002
    Applicant: Intel Corporation.
    Inventors: Richard H. Livengood, Paul Winer, Gary Woods, Michael DiBattista
  • Patent number: 6355494
    Abstract: A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: March 12, 2002
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Gary Woods, Michael DiBattista
  • Patent number: 6355950
    Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: March 12, 2002
    Assignee: Intel Corporation
    Inventors: Richard H. Livengood, Paul Winer, Valuri R. M. Rao
  • Publication number: 20020020862
    Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.
    Type: Application
    Filed: September 12, 2001
    Publication date: February 21, 2002
    Inventors: Richard H. Livengood, Paul Winer, Valuri R.M. Rao
  • Patent number: 6316981
    Abstract: A method and apparatus for clocking an integrated circuit. The apparatus includes an integrated circuit having a clock driver disposed in a first side of a semiconductor substrate, and a clock distribution network coupled to the clock driver and disposed in a second side of the semiconductor substrate to send a clock signal to clock an area of the integrated circuit.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: November 13, 2001
    Assignee: Intel Corporation
    Inventors: Valluri R. Rao, Jeffrey K. Greason, Richard H. Livengood
  • Patent number: 6309897
    Abstract: A method and an apparatus providing a circuit edit structure to an integrated circuit enabling circuit edits to be performed through the back side of an integrated circuit die. In one embodiment, a passive diffusion is disposed in the substrate of a flip-chip packaged integrated circuit die. A plurality of contacts couple the passive diffusion to a signal line disposed in a dielectric isolation layer of the integrated circuit die. In another embodiment, the signal line includes an uninterrupted length of approximately 3.0 microns beneath a field oxide region in the integrated circuit die, which provides a circuit edit cut location. The passive diffusion and circuit edit cut locations may be accessed through the back side of the flip-chip packaged integrated circuit, which enable circuit edits to be performed on the flip-chip packaged integrated circuit.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: October 30, 2001
    Assignee: Intel Corporation
    Inventor: Richard H. Livengood