Patents by Inventor Richard J. Ferguson
Richard J. Ferguson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11861181Abstract: Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.Type: GrantFiled: August 10, 2022Date of Patent: January 2, 2024Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: David D. Moser, Richard J. Ferguson, Daniel L. Stanley
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Publication number: 20220141237Abstract: A method of detecting abnormal or malicious activity in a point-to-point or packet-switched data communication network includes tapping a link in the network to obtain a data stream transmitted from a node of the network in parallel with transmission of the data stream through the network. The tap is non-invasive because it does not interfere with the normal traversal of the data stream across the network. This is useful for certain applications, such as mission-critical systems, where it is desirable to monitor the network and inspect the data without adversely impacting or otherwise interfering with the normal operation of the system. The method further includes decoding a communication protocol encoded in the data stream to obtain payload data from the data stream, analyzing the payload data to detect abnormal or malicious activity, and notifying a host of the network of the detected abnormal or malicious activity in the payload data.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Richard J. Ferguson, Michael Bear, Sumit Ray, Jeannine Robertazzi, Daniel L. Stanley
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Patent number: 11251601Abstract: Techniques are provided for non-volatile detection of an overvoltage condition in a circuit of interest. A circuit implementing the techniques according to an embodiment includes a fuse configured to provide a non-volatile indication of an overvoltage event, the indication associated with an open state of the fuse. The circuit also includes a voltage controlled current switch coupled in series to the fuse. The voltage controlled current switch is configured to enable current flow through the fuse in response to a supply voltage exceeding a threshold value associated with the overvoltage event. The current causes the fuse to switch from a closed state to an open state providing a non-volatile record of the overvoltage event. In some embodiments, the voltage controlled current switch can be a Zener diode with a breakdown voltage based on the threshold value, or a transistor configured to switch into conducting mode at the threshold value.Type: GrantFiled: April 14, 2020Date of Patent: February 15, 2022Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Richard J. Ferguson, Richard Brosh, William C. Singleton
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Publication number: 20210320489Abstract: Techniques are provided for non-volatile detection of an overvoltage condition in a circuit of interest. A circuit implementing the techniques according to an embodiment includes a fuse configured to provide a non-volatile indication of an overvoltage event, the indication associated with an open state of the fuse. The circuit also includes a voltage controlled current switch coupled in series to the fuse. The voltage controlled current switch is configured to enable current flow through the fuse in response to a supply voltage exceeding a threshold value associated with the overvoltage event. The current causes the fuse to switch from a closed state to an open state providing a non-volatile record of the overvoltage event. In some embodiments, the voltage controlled current switch can be a Zener diode with a breakdown voltage based on the threshold value, or a transistor configured to switch into conducting mode at the threshold value.Type: ApplicationFiled: April 14, 2020Publication date: October 14, 2021Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Richard J. Ferguson, Richard Brosh, William C. Singleton
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Patent number: 11139217Abstract: A method for modifying a portion of a substrate after production is described herein. The method can include diagnosing a circuit operation error causing a malfunction, identifying a first contact on the substrate, and connecting, electrically, the first contact to a second contact with at least one trace. The trace is done with a focused ion beam. The method can include diagnosing an error on an operative area of a post-manufacture circuit board causing a malfunction; introducing a metal precursor into a focused ion beam chamber; ionizing the metal precursor by contacting it with a gallium ion beam into a conductive metal and a further ion; depositing a first portion of a conductive metal onto a substrate to form a first trace; and forming the first trace between the operative area and a non-operative area thereby connecting the operative area and the non-operative area.Type: GrantFiled: September 9, 2019Date of Patent: October 5, 2021Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Jeffrey A. Zimmerman, Landon J. Caley, Richard J. Ferguson
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Publication number: 20210129480Abstract: A lamination transfer article includes an elastomeric layer with a first major surface including an array of discrete microstructures separated by land areas, wherein the microstructures in the array have a top surface; a first tie layer overlying at least some of the top surfaces of the microstructures of the elastomeric layer, wherein the land areas on the first major surface are uncovered by the first tie layer; and a second layer on a second major surface of the elastomeric layer, wherein the second layer is chosen from a second tie layer and a polymeric carrier film.Type: ApplicationFiled: February 16, 2018Publication date: May 6, 2021Inventors: John D. Le, Michael Benton Free, Margot A. Branigan, Susan L. Kent, Michael L. Steiner, Robert M. Jennings, Richard J. Ferguson
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Patent number: 10962594Abstract: The system and method of using a debug interface recorder and replay unit for debugging and testing devices of interest such as integrated circuits by using a debug interface buffer controller to receive, record, and replay sequences of instructions to the integrated circuit. This is particularly useful for deployed devices that are difficult or dangerous to access. This is also beneficial for devices that cannot be reached (e.g., after launch). By recording sequences and storing them for later use, and by communicating commands and configuration settings to a device, system maintenance and troubleshooting is accomplished saving valuable time and money without requiring physical access to the device of interest.Type: GrantFiled: May 23, 2019Date of Patent: March 30, 2021Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Richard J. Ferguson, Marla J. Lassa, Dean Saridakis
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Publication number: 20210074595Abstract: A method for modifying an LGA package after production is described herein. Generally, a modification of an LGA package by shorting two contacts together via a trace made of a robust conductive metal such as tungsten or platinum. Specifically, the present disclosure relates to a method for modifying a LGA package shorting two contacts together using FIB deposition via a gallium ion beam.Type: ApplicationFiled: September 9, 2019Publication date: March 11, 2021Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Jeffrey A. Zimmerman, Landon J. Caley, Richard J. Ferguson
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Publication number: 20200371159Abstract: The system and method of using a debug interface recorder and replay unit for debugging and testing devices of interest such as integrated circuits by using a debug interface buffer controller to receive, record, and replay sequences of instructions to the integrated circuit. This is particularly useful for deployed devices that are difficult or dangerous to access. This is also beneficial for devices that cannot be reached (e.g., after launch). By recording sequences and storing them for later use, and by communicating commands and configuration settings to a device, system maintenance and troubleshooting is accomplished saving valuable time and money without requiring physical access to the device of interest.Type: ApplicationFiled: May 23, 2019Publication date: November 26, 2020Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.Inventors: Richard J. FERGUSON, Marla J. LASSA, Dean SARIDAKIS
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Patent number: 10700046Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.Type: GrantFiled: August 7, 2018Date of Patent: June 30, 2020Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Dale A Rickard, Jason F Ross, John T Matta, Richard J Ferguson, Alan F Dennis, Joseph R Marshall, Jr., Daniel L Stanley
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Publication number: 20200051961Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.Type: ApplicationFiled: August 7, 2018Publication date: February 13, 2020Inventors: Dale A. Rickard, Jason F. Ross, John T. Matta, Richard J. Ferguson, Alan F. Dennis, Joseph R. Marshall, JR., Daniel L. Stanley
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Patent number: 10521549Abstract: A method for providing a power estimation for an electronic system is disclosed. Initially, a system architecture of an electronic system design is initially developed, and the system architecture of the electronic system design is then converted to a power flow architecture of the electronic system design. For each power domain within the power flow architecture of the electronic system design, a power domain type is designated. Subsequently, power information are added to the power flow architecture of the electronic system. Finally, a power roll-up calculation is performed on the power flow architecture of the electronic system design in order to yield a final system power value for the electronic system design.Type: GrantFiled: September 6, 2018Date of Patent: December 31, 2019Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Richard J. Ferguson, Joseph R. Marshall, Jr., George A. Sawyer
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Patent number: 10488673Abstract: The present disclosure provides an integrated optical component array and method of making an integrated optical component array useful for projection devices or other optical devices. The integrated optical component array can be a PBS array fabricated such that the individual PBS cubes having several elements can be assembled in a massively parallel manner and then singulated as individual optical components, and can result in a large reduction in manufacturing cost.Type: GrantFiled: June 7, 2018Date of Patent: November 26, 2019Assignee: 3M Innovative Properties CompanyInventors: John D. Le, Andrew J. Ouderkirk, Joseph C. Carls, Cameron T. Murray, Richard J. Ferguson, Cory C. Barum
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Patent number: 10379369Abstract: The present disclosure provides an integrated optical component array and method of making an integrated optical component array useful for projection devices or other optical devices. The integrated optical component array can be a PBS array fabricated such that the individual PBS cubes having several elements can be assembled in a massively parallel manner and then singulated as individual optical components, and can result in a large reduction in manufacturing cost.Type: GrantFiled: June 7, 2018Date of Patent: August 13, 2019Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: John D. Le, Andrew J. Ouderkirk, Joseph C. Carls, Cameron T. Murray, Richard J. Ferguson, Cory C. Barum
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Publication number: 20180292667Abstract: The present disclosure provides an integrated optical component array and method of making an integrated optical component array useful for projection devices or other optical devices. The integrated optical component array can be a PBS array fabricated such that the individual PBS cubes having several elements can be assembled in a massively parallel manner and then singulated as individual optical components, and can result in a large reduction in manufacturing cost.Type: ApplicationFiled: June 7, 2018Publication date: October 11, 2018Inventors: John D. Le, Andrew J. Ouderkirk, Joseph C. Carls, Cameron T. Murray, Richard J. Ferguson, Cory C. Barum
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Publication number: 20180284471Abstract: The present disclosure provides an integrated optical component array and method of making an integrated optical component array useful for projection devices or other optical devices. The integrated optical component array can be a PBS array fabricated such that the individual PBS cubes having several elements can be assembled in a massively parallel manner and then singulated as individual optical components, and can result in a large reduction in manufacturing cost.Type: ApplicationFiled: June 7, 2018Publication date: October 4, 2018Inventors: John D. Le, Andrew J. Ouderkirk, Joseph C. Carls, Cameron T. Murray, Richard J. Ferguson, Cory C. Barum
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Patent number: 10018850Abstract: The present disclosure provides an integrated optical component array and method of making an integrated optical component array useful for projection devices or other optical devices. The integrated optical component array can be a PBS array fabricated such that the individual PBS cubes having several elements can be assembled in a massively parallel manner and then singulated as individual optical components, and can result in a large reduction in manufacturing cost.Type: GrantFiled: December 11, 2014Date of Patent: July 10, 2018Assignee: 3M Innovative Properties CompanyInventors: John D. Le, Andrew J. Ouderkirk, Joseph C. Carls, Cameron T. Murray, Richard J. Ferguson, Cory C. Barum
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Publication number: 20160313566Abstract: The present disclosure provides an integrated optical component array and method of making an integrated optical component array useful for projection devices or other optical devices. The integrated optical component array can be a PBS array fabricated such that the individual PBS cubes having several elements can be assembled in a massively parallel manner and then singulated as individual optical components, and can result in a large reduction in manufacturing cost.Type: ApplicationFiled: December 11, 2014Publication date: October 27, 2016Applicant: 3M INOVATIVE PROPERTIES COMPANYInventors: John D. Le, Andrew J. Ouderkirk, Joseph C. Carls, Cameron T. Murray, Richard J. Ferguson, Cory C. Barum