Patents by Inventor Richard J. Hill

Richard J. Hill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563031
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Richard J. Hill
  • Patent number: 11557608
    Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Byeung Chul Kim, Francois H. Fabreguette, Richard J. Hill, Shyam Surthi
  • Publication number: 20230010799
    Abstract: Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 12, 2023
    Inventors: Lifang Xu, Richard J. Hill, Indra V. Chary, Lars P. Heineck
  • Patent number: 11527550
    Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Richard J. Hill, John D. Hopkins, Collin Howder
  • Patent number: 11527620
    Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Deepak Chandra Pandey, Haitao Liu, Richard J. Hill, Guangyu Huang, Yunfei Gao, Ramanathan Gandhi, Scott E. Sills
  • Publication number: 20220384242
    Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Sidhartha Gupta, David Ross Economy, Richard J. Hill, Kyle A. Ritter, Naveen Kaushik
  • Patent number: 11514953
    Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiaki Fukuzumi, Paolo Tessariol, David H. Wells, Lars P. Heineck, Richard J. Hill, Lifang Xu, Indra V. Chary, Emilio Camerlenghi
  • Patent number: 11467466
    Abstract: A display device (30) comprises a reflective display (38) arranged to render a first image viewable through a viewing surface and a projection means (31-37) arranged to render a second image viewable in reflection on the viewing surface, the reflective display (38) and the projection means (31-37) being mounted on a common frame.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 11, 2022
    Assignee: E Ink Corporation
    Inventors: Richard J. Paolini, Jr., Randal M. Hill
  • Publication number: 20220320136
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.
    Type: Application
    Filed: June 10, 2022
    Publication date: October 6, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Richard J. Hill, Yi Fang Lee, Martin C. Roberts
  • Publication number: 20220310831
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Publication number: 20220310637
    Abstract: Some embodiments include an integrated transistor having an active region comprising semiconductor material. A conductive gating structure is adjacent to the active region. The conductive gating structure includes an inner region proximate the active region and includes an outer region distal from the active region. The inner region includes a first material containing titanium and nitrogen, and the outer region includes a metal-containing second material. The second material has a higher conductivity than the first material. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Aaron Michael Lowe, Zhuo Chen, Marko Milojevic, Timothy A. Quick, Richard J. Hill, Scott E. Sills
  • Patent number: 11456208
    Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sidhartha Gupta, David Ross Economy, Richard J. Hill, Kyle A. Ritter, Naveen Kaushik
  • Publication number: 20220262820
    Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Matthew J. King, David A. Daycock, Yoshiaki Fukuzumi, Albert Fayrushin, Richard J. Hill, Chandra S. Tiwari, Jun Fujiki
  • Patent number: 11404440
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Richard J. Hill, Yi Fang Lee, Martin C. Roberts
  • Publication number: 20220238684
    Abstract: Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 28, 2022
    Inventors: Michael A. Lindemann, Collin Howder, Yoshiaki Fukuzumi, Richard J. Hill
  • Patent number: 11393920
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Patent number: 11381529
    Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums which provide for an agent support application with a plurality of plug-in communication support assistants. Each of the plurality of plug-in communication support assistants monitors communications between the agents and customers for different conversational triggers. Conversational triggers may be any conversation, either by the agent or the customer, that the communication support assistant is trained to detect. Upon detecting one of these conversational triggers, the plug-in communication support assistant provides one or more suggestions to the agent.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 5, 2022
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Kimarie Pike Matthews, Richard Castanho, Germaine S. Chee, Robin J. Cusimano, Brett D. Ehrlich, Tyua Larsen Fraser, Colleen Reardon Graham, Gregory Scott Hill, James W. Pedersen, Timothy J. Shipman
  • Publication number: 20220199645
    Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Changhan Kim, Chet E. Carter, Cole Smith, Collin Howder, Richard J. Hill, Jie Li
  • Publication number: 20220199641
    Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
  • Patent number: D957399
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: July 12, 2022
    Assignee: Apple Inc.
    Inventors: Jody Akana, Molly Anderson, Bartley K. Andre, Shota Aoyagi, Anthony Michael Ashcroft, Marine C. Bataille, Jeremy Bataillou, James A. Bertin, Daniele De Iuliis, Markus Diebel, David J. Dunsmoor, M. Evans Hankey, Matthew David Hill, Julian Hoenig, Richard P. Howarth, Stoyan P. Hristov, Jonathan P. Ive, Julian Jaede, Duncan Robert Kerr, David A. Pakula, Peter Russell-Clarke, Benjamin Andrew Shaffer, Mikael Silvanto, Ian Spraggs, Christopher J. Stringer, Joe Sung Ho Tan, Tang Yew Tan, Clement Tissandier, Melissa A. Wah, Eugene Antony Whang, Rico Zörkendörfer