Abstract: Genetically modified non-human animals are provided that may be used to model human hematopoietic cell development, function, or disease. The genetically modified non-human animals comprise a nucleic acid encoding human IL-6 operably linked to an IL-6 promoter. In some instances, the genetically modified non-human animal expressing human IL-6 also expresses at least one of human M-CSF, human IL-3, human GM-CSF, human SIRPa or human TPO. In some instances, the genetically modified non-human animal is immunodeficient. In some such instances, the genetically modified non-human animal is engrafted with healthy or diseased human hematopoietic cells. Also provided are methods for using the subject genetically modified non-human animals in modeling human hematopoietic cell development, function, and/or disease, as well as reagents and kits thereof that find use in making the subject genetically modified non-human animals and/or practicing the subject methods.

Abstract: Genetically modified non-human animals expressing human EPO from the animal genome are provided. Also provided are methods for making non-human animals expressing human EPO from the non-human animal genome, and methods for using non-human animals expressing human EPO from the non-human animal genome. These animals and methods find many uses in the art, including, for example, in modeling human erythropoiesis and erythrocyte function; in modeling human pathogen infection of erythrocytes; in in vivo screens for agents that modulate erythropoiesis and/or erythrocyte function, e.g. in a healthy or a diseased state; in in vivo screens for agents that are toxic to erythrocytes or erythrocyte progenitors; in in vivo screens for agents that prevent against, mitigate, or reverse the toxic effects of toxic agents on erythrocytes or erythrocyte progenitors; in in vivo screens of erythrocytes or erythrocyte progenitors from an individual to predict the responsiveness of an individual to a disease therapy.

Abstract: A compact hyperspectral imager adapted to operate in harsh environments and to conduct post acquisition signal processing to provide automated and improved hyperspectral processing results is disclosed. The processing includes luminance and brightness processing of captured hyperspectral images, hyperspectral image classification and inverse rendering to produce luminance invariance image processing.

Abstract: A compact hyperspectral imager adapted to operate in harsh environments and to conduct post acquisition signal processing to provide automated and improved hyperspectral processing results is disclosed. The processing includes luminance and brightness processing of captured hyperspectral images, hyperspectral image classification and inverse rendering to produce luminance invariance image processing.

Abstract: A compact hyperspectral imager adapted to operate in harsh environments and to conduct post acquisition signal processing to provide automated and improved hyperspectral processing results is disclosed. The processing includes luminance and brightness processing of captured hyperspectral images, hyperspectral image classification and inverse rendering to produce luminance invariance image processing.

Abstract: The present invention relates to a method for treating a lignocellulose biomass in order to dissolve the lignin therein, while the cellulose does not dissolve. The cellulose pulp obtained can be used to produce glucose. In addition the lignin can be isolated for subsequent use in the renewable chemical industry as a source for aromatic platform chemicals.

Abstract: The present invention relates to a method for treating a lignocellulose biomass in order to dissolve the lignin therein, while the cellulose does not dissolve. The cellulose pulp obtained can be used to produce glucose. In addition the lignin can be isolated for subsequent use in the renewable chemical industry as a source for aromatic platform chemicals.

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Abstract: A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Abstract: The present invention is in the field of soybean variety S06-M03256 breeding and development. The present invention particularly relates to the soybean variety S06-M03256 and its progeny, and methods of making S06-M03256.

Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013?1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface.

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Abstract: A method is disclosed for forming an epitaxial layer on a front side of a substrate formed of a monocrystalline material, using a chemical vapor deposition system. In this method, a plurality of gettering wafers formed of a gettering material are arranged in the CVD system, such that the front side of each substrate is facing one of the gettering wafers. Impurities present in the CVD system during formation of the epitaxial layer are gettered by the gettering wafers. Alternatively, a layer of a gettering material is deposited on a back side of each of the plurality of substrates, and the substrates are arranged such that the front side of each substrate is facing the backside of another of the substrates. In another embodiment, a layer of a gettering material is deposited on an interior surface of the CVD system. Impurities removed from the CVD system during epitaxial formation include oxygen, water vapor and other oxygen-containing contaminants.