Patents by Inventor Richard Joseph McPartland

Richard Joseph McPartland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7764541
    Abstract: One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: July 27, 2010
    Assignee: Agere Systems Inc.
    Inventors: Ross Alan Kohler, Richard Joseph McPartland, Ranbir Singh
  • Patent number: 7460424
    Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: December 2, 2008
    Assignee: Agere Systems Inc.
    Inventors: Dennis E. Dudeck, Donald Albert Evans, Richard Joseph McPartland, Hai Quang Pham
  • Patent number: 7254763
    Abstract: A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: August 7, 2007
    Assignee: Agere Systems Inc.
    Inventors: Duane Rodney Aadsen, Ilyoung I. Kim, Ross Alan Kohler, Richard Joseph McPartland
  • Patent number: 7177212
    Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: February 13, 2007
    Assignee: Agere Systems Inc.
    Inventors: Dennis E. Dudeck, Donald Albert Evans, Richard Joseph McPartland, Hai Quang Pham
  • Patent number: 7085149
    Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by applying a biased gate voltage (relative to a source voltage) to the gate of at least one of transistor in the array. The biased gate voltage is applied at least during a precharge phase of a read cycle. When the array transistors are n-channel transistors, the biased voltage is a negative bias voltage (relative to the source voltage). When the array transistors are p-channel transistors, the biased voltage is a positive bias voltage (relative to the source voltage). Applying a negative backgate bias to the transistor's p-well contact can also reduce n-channel transistor subthreshold leakage current. Thus, for an n-channel array, a negative gate voltage and backgate bias (optional) are applied to cell transistors in the off state.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: August 1, 2006
    Assignee: Agere Systems Inc.
    Inventors: Dennis E. Dudeck, Donald Albert Evans, Ross Alan Kohler, Richard Joseph McPartland, Hai Quang Pham
  • Patent number: 7042779
    Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: May 9, 2006
    Assignee: Agere Systems Inc.
    Inventors: Dennis E. Dudeck, Donald Albert Evans, Richard Joseph McPartland, Hai Quang Pham
  • Patent number: 6879509
    Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: April 12, 2005
    Assignee: Agere Systems, Inc.
    Inventors: Donald A. Evans, Ross Alan Kohler, Nghia Q. Lam, Richard Joseph McPartland, Hai Quang Pham
  • Publication number: 20040233693
    Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 25, 2004
    Applicant: Agere Systems, Inc.
    Inventors: Donald A. Evans, Ross Alan Kohler, Nghia Q. Lam, Richard Joseph McPartland, Hai Quang Pham
  • Patent number: 6512700
    Abstract: A non-volatile memory cell and associated cell array and memory device having reduced program disturb, improved retention of programmed information, and reduced power consumption are disclosed. The memory cell includes a control device coupled to a switch device via a common floating gate, with the control device and the switch device formed on a common substrate, and the switch device formed at least in part in a tub region on the substrate. The tub region has a contact region formed therein. The contact region is adapted for application of a bias voltage to the tub region during a programming operation of the memory cell so as to reduce a programming voltage required to program the memory cell. In an illustrative embodiment, a drain-to-substrate voltage required to program the memory cell is reduced from a conventional value of about 6.5 volts to a value of about 3.5 volts, thus alleviating program disturb problems that can result, e.g.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: January 28, 2003
    Assignee: Agere Systems Inc.
    Inventors: Richard Joseph McPartland, Ranbir Singh
  • Patent number: 6459615
    Abstract: A non-volatile memory device is disclosed which includes an erase device that is shared among an array of memory cells. Each of the memory cells in the array includes a control device coupled to a switch device via a common floating gate. Each of at least a subset of the memory cells further includes a portion of the shared erase device, the portion of the shared erase device associated with a given one of the memory cells being coupled to the switch device of that cell via the floating gate of that cell. The shared erase device is utilizable in performing an erase operation for each of the memory cells associated therewith. Advantageously, the use of the shared erase device substantially reduces the circuit area requirements of the memory array. The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: October 1, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Richard Joseph McPartland, Ranbir Singh
  • Patent number: 6191963
    Abstract: An integrated circuit-based charge pump generates an output voltage having a greater magnitude than a power supply voltage. The charge pump has a charge pump section having a plurality of alternating stages driven by first and second alternating, non-overlapping clock signals, said plurality of alternating stages including an input stage for receiving the power supply voltage and an output stage for generating at a last stage node a last stage voltage having a greater magnitude than the power supply voltage. A gating transistor is coupled at a drain terminal to the last stage node, wherein the gating transistor is clocked by one of said clock signals and is biased so that the gating transistor, during a boost phase, gates the last stage voltage to a load coupled to the source terminal of the gating transistor without a voltage drop and, at other times, turns off to prevent charge from flowing from the load into the last stage node of the charge pump section.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: February 20, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Richard Joseph McPartland, Amit Kumar Banerjee, Duane J. Loeper
  • Patent number: 6104176
    Abstract: The voltage regulator includes a regulator circuit, connected between a high potential and a low potential, regulating an output voltage based on an input voltage. The regulator circuit includes a changing circuit which changes at least one of a voltage range of the output voltage and a rate at which the output voltage changes with respect to changes in the input voltage. The changing circuit selectively increases a maximum value of the voltage range of the output voltage, and also selectively increases the rate at which the output voltage changes with respect to changes in the input voltage.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: August 15, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Richard Joseph McPartland, Amit Kumar Banerjee
  • Patent number: 6091657
    Abstract: When flash memory devices are scaled down into the deep-submicron regime, tub erase is being increasingly deployed because it features lower erase current and better reliability performance than the conventional source-side erase scheme. However, tub erase requires higher voltages to be applied to the flash memory device. In a typical design, during tub erase 10 to 12 volts is applied to the tub, source and drain, and -6V is applied to the control gate of the flash memory device. However, in the state-of-the-art CMOS processes (usually used at a power supply voltage 3.3 V and below), it is difficult to build high voltage (HV) devices to support source/drain voltages of more than 6 volts unless the process complexity is significantly increased. Therefore, the required HV devices prevent tub erase from being widely used, especially for embedded applications.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: July 18, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Chun Chen, Richard Joseph McPartland
  • Patent number: 6084804
    Abstract: An integrated circuit memory array has a plurality of rows of memory cells, each row of memory cells being coupled to a respective row line for enabling the memory cells of the row. A row driver of the memory array provides a row voltage on the row line. A pull-up transistor of the row driver pulls up the row voltage in response to a row control signal. A parasitic diode of the pull-up transistor is coupled at its anode to the row line and is adapted to pull the row voltage down from a high state voltage to a diode drop voltage plus a low state voltage in response an enable block signal coupled to the cathode of the parasitic diode. A pull-down transistor of the row driver also pulls down the row voltage in response to the row control signal.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: July 4, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: Richard Joseph McPartland
  • Patent number: 5889704
    Abstract: A semiconductor EEPROM memory cell having a control circuit and an internal memory device for providing high speed electronic data storage (i.e. writing binary 1 and 0 functionality) in a relatively small physical area. In general, internal memory device has a floating gate, and a source, a drain and a gate coupled to the control circuit. In operation, the control circuit provides electrical signals to the source, drain and gate to control the writing of electrical data to and reading of electrical data from the internal memory device. When writing data to the memory device the control circuit provides electrical signals to the source, drain and gate to initiate electron tunneling between the floating gate and drain, wherein the electron tunneling ultimately produces a conductive or nonconductive state representing the data stored by the internal memory device.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: March 30, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Richard Joseph McPartland