Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: In an example, a circuit includes a first comparator, a second comparator, a pulse counter, a processor, a first ADC, and a second ADC. The first comparator has a first input coupled to a first node, a second input, and an output. The second comparator has a first input coupled to a second node, a second input, and an output. A first DAC is coupled to the second input of the first comparator. A second DAC is coupled to the second input of the second comparator. The pulse counter has a first input coupled to the output of the first comparator and a second input coupled to the output of the second comparator. The first ADC has an input coupled to the first node and an output coupled to the processor. The second ADC has an input coupled to the second node and an output coupled to the processor.

Abstract: A method of determining a direction of rotation of a shaft is disclosed, as well as an integrated circuit chip that uses the disclosed method. The method includes receiving a first binary signal and a second binary signal from a transducer attached to the shaft, with the first and second binary signals being in quadrature. A present quadrant identification number, QIDPRESENT, is determined as a two-digit binary number by left-shifting a value of the first signal and adding a value of the second signal. After a sampling interval has elapsed, the method sets a past quadrant identification number, QIDPAST, to the value of said QIDPRESENT, determines a new value of QIDPRESENT and calculates a value of a transition code using an equation that operates on QIDPRESENT and QIDPAST. The method uses the transition code to determine a direction of rotation of the shaft.

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Abstract: A method of determining a direction of rotation of a shaft is disclosed, as well as an integrated circuit chip that uses the disclosed method. The method includes receiving a first binary signal and a second binary signal from a transducer attached to the shaft, with the first and second binary signals being in quadrature. A present quadrant identification number, QIDPRESENT, is determined as a two-digit binary number by left-shifting a value of the first signal and adding a value of the second signal. After a sampling interval has elapsed, the method sets a past quadrant identification number, QIDPAST, to the value of said QIDPRESENT, determines a new value of QIDPRESENT and calculates a value of a transition code using an equation that operates on QIDPRESENT and QIDPAST. The method uses the transition code to determine a direction of rotation of the shaft.

Abstract: A method of determining a direction of rotation of a shaft is disclosed, as well as an integrated circuit chip that uses the disclosed method. The method includes receiving a first binary signal and a second binary signal from a transducer attached to the shaft, with the first and second binary signals being in quadrature. A present quadrant identification number, QIDPRESENT, is determined as a two-digit binary number by left-shifting a value of the first signal and adding a value of the second signal. After a sampling interval has elapsed, the method sets a past quadrant identification number, QIDPAST, to the value of said QIDPRESENT, determines a new value of QIDPRESENT and calculates a value of a transition code using an equation that operates on QIDPRESENT and QIDPAST. The method uses the transition code to determine a direction of rotation of the shaft.

Abstract: A method of determining a direction of rotation of a shaft is disclosed, as well as an integrated circuit chip that uses the disclosed method. The method includes receiving a first binary signal and a second binary signal from a transducer attached to the shaft, with the first and second binary signals being in quadrature. A present quadrant identification number, QIDPRESENT, is determined as a two-digit binary number by left-shifting a value of the first signal and adding a value of the second signal. After a sampling interval has elapsed, the method sets a past quadrant identification number, QIDPAST, to the value of said QIDPRESENT, determines a new value of QIDPRESENT and calculates a value of a transition code using an equation that operates on QIDPRESENT and QIDPAST. The method uses the transition code to determine a direction of rotation of the shaft.