Patents by Inventor Richard N. Mendelson

Richard N. Mendelson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5568614
    Abstract: A data handling arrangement for a computer system, with particular application to multimedia systems, allows device adapters (control units) attached to the system to autonomously (without interrupting the system processor) control processing of a data stream of arbitrary length through memory buffers which are smaller than the stream. In this (stream processing) operation, data constituting the data stream flows through devices controlled by the adapter in succession, and is held in shared memory buffers as it passes between devices. The adapters are prepared for the stream processing operation by a system processor, indicate their preparation status to the processor, receive an initiating signal from the processor, and then proceed to direct the operation to completion without further assistance from the processor. In the operation, the adapters coordinate usage of the memory buffers by respective devices.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: October 22, 1996
    Assignee: International Business Machines Corporation
    Inventors: Richard N. Mendelson, Ralph M. Pipitone
  • Patent number: 5481724
    Abstract: A coded logical interrupt signal is sent between system or subsystem units in a data processing system. The logical interrupt is sent by a sending unit, that requests the interrupt, and is sent to a receiving unit that the sending unit wishes to interrupt. These coded logical interrupts are accumulated in the receiving unit. When the receiving unit is actually physically interrupted by control of the processor in the unit, all logical interrupts that have been accumulated are processed. The logical interrupt may be coded to indicate sending unit, that is the source of the interrupt, and the action being requested by the sending unit. If the interrupt includes only source information, the action information is sent separately by the sending unit to memory in the receiving unit. If the interrupt includes both source identification and action information, the receiving unit can interpret source and action directly from the interrupt.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: January 2, 1996
    Assignee: International Business Machines Corp.
    Inventors: Arthur J. Heimsoth, Ernest N. Mandese, Joseph P. McGovern, Richard N. Mendelson
  • Patent number: 5265255
    Abstract: This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus.
    Type: Grant
    Filed: September 24, 1990
    Date of Patent: November 23, 1993
    Assignee: International Business Machines Corp.
    Inventors: Francis M. Bonevento, Ernest N. Mandese, Richard N. Mendelson
  • Patent number: 5185864
    Abstract: A computing system including a host processor and at least one intelligent subsystem having attached devices, has two interrupt ports. The one intelligent subsystem and the attached devices are each viewed as a logical device by the host processor, and each is assigned a device identification number. The host processor provides direct and indirect commands to the logical devices. For direct commands, first physical interrupts are provided to the host processor serially from the logical devices through an Interrupt Status Port. For indirect commands, logical interrupts are stored in predetermined bit positions in a Device Interrupt Indentifier Port (DIIP) in accordance with the device identification numbers. A second single physical interrupt is provided to the host processor as long as there is at least one logical interrupt pending from at least one logical device as the result of an indirect command.
    Type: Grant
    Filed: June 16, 1989
    Date of Patent: February 9, 1993
    Assignee: International Business Machines Corporation
    Inventors: Francis M. Bonevento, Chester A. Heath, Ernest N. Mandese, Richard N. Mendelson
  • Patent number: 5170471
    Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.
    Type: Grant
    Filed: January 6, 1992
    Date of Patent: December 8, 1992
    Assignee: International Business Machines Corporation
    Inventors: Francis M. Bonevento, Douglas R. Chrisholm, Sammy D. Dodds, Dhruvkumar M. Desai, Ernest N. Mandese, Andrew B. McNeill, Richard N. Mendelson
  • Patent number: 5131082
    Abstract: A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.
    Type: Grant
    Filed: June 9, 1989
    Date of Patent: July 14, 1992
    Assignee: International Business Machines Corporation
    Inventors: Francis M. Bonevento, Douglas R. Chisholm, Sammy D. Dodds, Dhruvkumar M. Desai, Ernest N. Mandese, Andrew B. McNeill, Richard N. Mendelson
  • Patent number: 4514823
    Abstract: There is disclosed apparatus and a method for extending a parallel channel of the host processor over a serial link to a remote peripheral device. The apparatus includes a microprocessor within I/O channel extension logic which responds to either instructions or data from a host processor. The instructions are of the type commanding the I/O device to perform a specific operation and the data is provided in response to requests for data from the I/O device. The channel extension logic is coupled to the host processor's channel and thus is able to obtain data from the host storage by cycle steal techniques. Within the channel extension logic are means to serialize the information and transmit it in a serial manner over the link. The microprocessor within the channel extension logic creates a frame, including a control byte, which identifies the type of information followed by the data, which frame is then communicated over the serial link to the I/O device.
    Type: Grant
    Filed: January 15, 1982
    Date of Patent: April 30, 1985
    Assignee: International Business Machines Corporation
    Inventors: Richard N. Mendelson, Douglas M. O'Neal, Leo A. Sharp, Jr.
  • Patent number: 4268906
    Abstract: An I/O controller is provided for transferring data between a host processor and a plurality of I/O devices wherein the host processor generates a transfer command and each of the plurality of I/O devices generates multiple asynchronous service requests for transfer to the host processor. Control circuitry is provided for controlling the transfer of the service requests from the plurality of I/O devices to the host processor. The control circuitry generates a host processor interrupt signal for application to the host processor, such that in response to the host processor interrupt signal, the host processor generates the transfer command to allow the control circuitry to transfer the service requests to the host processor.
    Type: Grant
    Filed: December 22, 1978
    Date of Patent: May 19, 1981
    Assignee: International Business Machines Corporation
    Inventors: Donall G. Bourke, Richard N. Mendelson, Luis Madruga