Abstract: A system for measuring a heat response of a battery cell includes a cell chamber configured to receive the battery cell therein. The cell chamber is configured to trigger a battery cell into a thermal runaway event while in the cell chamber, which causes the battery cell to eject an electrode winding, particles, and gas. The system also includes an ejecta bore muffler configured to receive the electrode winding, the particles, and the gas. The system also includes an ejecta basket configured to be positioned at least partially within the ejecta bore muffler. The ejecta basket is configured to capture the electrode winding while allowing at least a portion of the particles, the gas, or both to pass therethrough. The system also includes a gas collection system configured to receive at least a portion of the gas that passes through the ejecta basket.

Abstract: A method and apparatus to selectively allow communication and information exchange between a user and an ally in a networked communication system that includes mobile devices, laptop computers, and computers. The user selects from a list of relationship descriptors, and trust levels are designated responsive to the relationship descriptors. The list of relationship descriptors may include one or more high level group descriptors and lower level descriptors. The user may select a privacy level, and responsive to the trust level and the privacy level, communication and information sharing are selectively allowed. The information shared may include user profile information, an ally list, favorites, shared interests, and calendars. A social fabric diagram is created from which the user may view ally relationships.

Abstract: The present invention comprises novel methods for the use of compositions comprising 7-keto DHEA for treating psychiatric conditions. These methods include administering an effective amount of a composition comprising 7-keto DHEA in an acceptable carrier, alone or in combination with other psychiatric drugs, such as analgesic agents, anticonvulsants, anti-anxiety agents, antidepressants, anti-panic agents, antipsychotic agents, bipolar agents, psychostimulants to reduce or ameliorate symptoms of a psychiatric condition. This method may be used alone or as an adjunctive treatment for treating a wide variety of psychiatric conditions such as stress disorders, anxiety disorders and depressive disorders.

Abstract: The present invention relates to the use of 3-acetyl-7-oxo-dehydroepiandrosterone (7-keto DHEA) in the preparation of a medicament to treat or ameliorate psychiatric conditions. The present invention relates to methods of using compositions comprising 7-keto DHEA to treat or ameliorate psychiatric conditions. These methods include administering an effective amount of a composition comprising 7-keto DHEA in an acceptable carrier, alone or in combination with other psychiatric drugs to reduce or ameliorate symptoms of a psychiatric condition. This method may be used alone or as an adjunctive treatment for treating a wide variety of psychiatric conditions.

Abstract: A holder for implements such as a mortal board, which is to be horizontally positioned, knives, such as broad, spackle, and shear knives, which are to be positioned at an angle, and a roll of drywall tape, vertically positioned. Holder comprises a back plate to secure implements, and a second plate in which the implement holder is temporarily attached to the user, more specifically, the waist area of the user. The mortar board is inserted into the Y-shaped slots which are horizontally aligned to the back plate and are disposed in spaced relationship. The knives are inserted into the compression loaded slots having adjacent relationship and positioned at an angle from the back plate. The tape is inserted into the J-shaped hook which is spaced away from the back plate to allow for the tapes positioning and removal to and from the implement holder. The parts which comprise the implement holder are made from a rigid material, preferably aluminum.

Abstract: The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.

Abstract: A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

Abstract: A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.

Abstract: A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.

Abstract: A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.

Abstract: A retaining ring (30) for use in combination with a wheel rim (10) having a separable bead flange (14) to secure the separable bead flange on the rim in the absence of a properly inflated tire is characterized by an inboard facing portion (30a) and an outboard facing portion (30b) and a split in the ring defining terminal ends, (32,33) each terminal end having a circumferentially oriented first bore (36,37) in the inboard facing portion (30a) and a second bore (38,39) in the outboard facing portion (30b) at an angular relationship with respect to the first bore.

Abstract: A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

Abstract: A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.

Abstract: A miniature DIP switch (10) has actuator levers (82) projecting from a side of the housing (12). A plurality of cantilevered moveable contact arms (72) are supported by a section (34) of the base (30), and a plurality of oppositely disposed cantilevered contact arms (62) are supported by a complementary section (32) of the base. A plurality of insulative rotatable lever actuators (80) are supported each by a respective moveable contact arm (72). Each actuator (80) comprises a lever (82) projecting from a respective opening (18) In the housing (12), an arcuate bearing surface (86) engaging an arcuately shaped boss (22) in the housing, a pair of depending side walls (88) each having arcuately shaped ends (90), and a cam protrusion (87) disposed between the depending side walls (88) and engaging its respective moveable contact arm (72).

Abstract: In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request.

Abstract: In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.

Abstract: The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.

Abstract: A liquid-lubricated roll has an annular roller element rotatably supported by anti-friction bearings on an elongated axle which is longitudinally curved. Liquid lubricant for the bearings is supplied to an annular passageway between the roller element and the axle. During rotation of the roller, the liquid forms into a thin annular layer on its inner surface, which is agitated by projections on the axle to produce a lubricating mist.Barrier rings placed adjacent to the bearings are adapted to permit liquid to flow along the passageway while the roll is rotating, but to block flow of liquid above a selected level when the roll is stationary. This maintains a more uniform longitudinal distribution of liquid within the roll during periods of disuse, so that none of the bearings will be flooded when rotation starts, and a saving in power consumption and bearing life will therefore be realized.