Abstract: A method, apparatus and computer-readable storage medium for regulating packet flow through a device such as a router with a switch fabric. Congestion information, such as statistics on bandwidth utilization, is collected for each of a plurality of queues at an egress stage of the device. Based on the bandwidth utilization statistics, computations are performed to evaluate a “discard probability” for each queue. This information is transmitted to the ingress stage, either periodically or at other controlled time periods, such as when the discard probability changes significantly. The ingress stage can then proceed with controllable transmission or non-transmission of packets to the switch fabric, depending on the queue for which the packet is destined and also depending on the discard probability for that queue. In this way, congestion can be avoided even before it even has a chance to occur.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: Methods and apparatus for processing a plurality of sets of routing information received from corresponding ones of a plurality of neighbor nodes connectable to a router, the router having a plurality of memory units accessible via separate paths. The method comprises creating a respective plurality of non-identical routing information subsets from each of at least one of the received sets of routing information; accessing the plurality of memory units via the separate access paths; and storing the plurality of non-identical routing information subsets created from a given one of said received sets of routing information in respective ones of the plurality of memory units. By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Abstract: There is described a display comprising: a monolithic array of cells; and optical direct outputs located within the monolithic array of cells and adapted for collectively forming a human-readable display upon using a first portion of available light, wherein a second portion of the available light is used concurrently to the first portion for a purpose other than the forming the human-readable display.

Abstract: A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting data signals into the communications bus. The communications bus includes a plurality of parallel channels, and at least one channel crossover point associated with each cell. Each crossover point implements a regular change in a channel order of the communications bus, such that each access point is coupled to a channel of the communications bus. Propagation delays are reduced by inserting buffers at regular intervals along the length of each channel. An output buffer at a downstream boundary of each power domain of the system prevents undesired currents due to voltage mismatch. The propagation direction of data signals away from the access point, and propagation of data to an adjacent downstream cell can be controlled to reduce bus traffic and power consumption.

Abstract: A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Abstract: A microelectronic complex including a body of semi-conductor material containing an integrated circuit, and a plurality of contact pads on the body for receiving signal conducting members for connection to an external substrate. The contact pads allow signals to be exchanged between the integrated circuit and the external substrate via the signal conducting members. A majority of the contact pads are disposed on the body of the microelectronic complex according to a configuration whereby the stress effects on the signal conducting members caused by thermal expansion mismatch between the microelectronic complex and the external substrate are minimized. In a specific configuration, a majority of the contact pads form a cluster circumscribing a predetermined area of the microelectronic complex body, whereby the cluster is characterized by a minimum inter-pad distance among the majority of contact pads on the body of the microelectronic complex.

Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.

Abstract: A method and system for regulating packet flow to a downstream entity capable of forwarding packets to a plurality of intermediate destinations. The method includes maintaining a database of queues, each queue in the database being associated with packets intended to be forwarded to a corresponding one of a plurality of final destinations via a corresponding one of the intermediate destinations. Each queue in the database is further associated with a state that is either active or inactive. Upon receipt of a message from the downstream entity indicating a reduced (increased) ability of a particular one of the intermediate destinations to accept packets intended to be forwarded to a particular one of the final destinations, the method provides for rendering inactive (active) the state of the queue associated with packets intended to be forwarded to the particular final destination via the particular intermediate destination.

Abstract: A router includes a routing layer and a switching layer. The routing layer includes a plurality of I/O ports for exchanging data with components external to the router. The switching layer is adapted to switch data packets between I/O ports of the routing layer. The switching layer includes an array of cells in communication with the routing layer for permitting exchange of data packets between the array of cells and the routing layer. Each cell includes a memory for receiving a data packet from the routing layer. The routing layer includes a controller to control release of a data packet toward a cell of the array at least in part on a basis of a degree of occupancy of the memory in the cell.

Abstract: A microelectronic complex including a first body, a discrete functional module and an interconnection module. The first body is characterized by a planar main surface that defines an attachment site. The discrete functional module includes a second body containing an integrated circuit, the second body characterized by a pair of main faces and a side surface between the pair of main faces. The discrete functional module is affixed to the first body at the attachment site, such that the first and second bodies are maintained in a predetermined spatial relationship in which the side surface of the second body faces the planar main surface of the first body. The interconnection module allows signals to be transported between the first body and the integrated circuit of the second body.

Abstract: Method, apparatus and software for processing sets of routing information in a router having a plurality of memory units accessible via separate access paths. The sets of routing information are typically routes received from neighbour nodes. The method includes creating a plurality of non-identical routing information subsets from each received set of routing information, accessing the memory units via the separate access paths and storing the routing information subsets created from a common set of routing information in respective ones of the plurality of memory units, By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Abstract: An interconnect arrangement for an array of N discrete functional modules, including a data bus between the modules formed of N sets of connections where each respective module sends on a respective one of the N sets. Each module is capable of receiving from each of the N sets, and contains an arbitration unit that selects a single set to receive at a given time if more than one of the sets has data for that module at that given time. The N sets are interwoven such that they can be formed by multiple imprints of a single reticle on a given lithographic layer, while maintaining relatively uniform connection lengths.

Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, permitting an exchange of data packets between the cells of the array and an exchange of control information between the cells of the array. Each cell is operative to control transmission of data packets to other cells of the array at least in part on a basis of the control information. The control information is thus used to regulate the flow of data packets between cells.

Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of the array selected on a basis of the determined destination. Each cell further includes a plurality of receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets to the I/O interface.

Abstract: A conductive fabric including a plurality of conductive elements defining an alternating sequence of segments and cross-over regions. Within each of the segments, the conductive elements are arranged substantially in parallel; within each of the cross-over regions located between two adjacent segments, the conductive elements are permuted so as to allow the position occupied by at least one of the conductive elements to be different in each of the two adjacent segments. Between a pair of reference segments, each of the conductive elements experience coupling with respect to a subset of said conductive elements other than itself, the coupling experienced by each of the conductive elements being substantially identical.

Abstract: A cooling device for cooling a microelectronic complex including a plurality of discrete functional modules. The cooling device includes a plurality of independent cooling modules, each cooling module in a thermal exchange relationship with a respective one of the plurality of discrete functional modules. During operation of the microelectronic complex, a cooling requirement of each discrete functional module is dynamically assessed, and the amount of cooling provided by each cooling module is adjusted on the basis of the assessed cooling requirements. Thus, the discrete functional modules are cooled independently from one another.

Abstract: A massively parallel data processing system consisting of an array of closely spaced cells where each cell has direct output means as well as means for processing, memory and input. The data processing system according to the present invention overcomes the von Neumann bottleneck of uniprocessor architectures, the I/O and memory bottlenecks that plague parallel processors, and the input bandwidth bottleneck of high-resolution displays.

Abstract: The present invention provides a connector for transporting signals. The connector comprises a body made of a continuous body of material or alternatively of a plurality of superposed layers. The body includes a first terminal end, a second terminal end that is remote from the first terminal end and a three-dimensional arrangement of signal transmissive pathways within the body. The signal transmissive pathways are spaced apart from one another and extend side by side along a direction of propagation from the first terminal end to the second terminal end. The signal transmissive pathways are exposed at the first terminal end and at the second terminal end to allow external devices connected to the first terminal end and to the second terminal end to exchange signals via the signal transmissive pathways. The signal transmissive pathways are distributed in the body in multiple directions transverse to the direction of propagation.

Abstract: The present invention provides a semiconductor wafer that has a predetermined global functionality and comprises a top surface, a bottom surface and a peripheral edge between the top surface and the bottom surface. An integrated circuit is fabricated on the semiconductor wafer and includes a working set of discrete functional modules arranged into a central rectangular array of rows and columns defined by a boundary that includes four rectilinear sides and four corners. The integrated circuit further includes a spare set of discrete functional modules formed outside the boundary of the working set into at least one line that is disposed along a side of the rectangular array of the working set. If a discrete functional module in the working set is found to be defective, it can be replaced by a discrete functional module in the spare set.