Patents by Inventor Richard Vreeland
Richard Vreeland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047543Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.Type: ApplicationFiled: October 20, 2023Publication date: February 8, 2024Inventors: Rami HOURANI, Richard VREELAND, Giselle ELBAZ, Manish CHANDHOK, Richard E. SCHENKER, Gurpreet SINGH, Florian GSTREIN, Nafees KABIR, Tristan A. TRONIC, Eungnak HAN
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Patent number: 11887887Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: GrantFiled: June 27, 2022Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Patent number: 11837644Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.Type: GrantFiled: September 23, 2019Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Rami Hourani, Richard Vreeland, Giselle Elbaz, Manish Chandhok, Richard E. Schenker, Gurpreet Singh, Florian Gstrein, Nafees Kabir, Tristan A. Tronic, Eungnak Han
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Patent number: 11784123Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: GrantFiled: February 22, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20230187395Abstract: Embodiments herein relate to systems, apparatuses, or processes for hybrid bonding two dies, where at least one of the dies has a top layer to be hybrid bonded includes one or more copper pad and a top oxide layer surrounding the one or more copper pad, with another layer beneath the oxide layer that includes carbon atoms. The top oxide layer and the other carbide layer beneath may form a combination gradient layer that goes from a top of the top layer that is primarily an oxide to a bottom of the other layer that is primarily a carbide. The top oxide layer may be performed by exposing the carbide layer to a plasma treatment. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Inventors: Nafees A. KABIR, Jeffery BIELEFELD, Manish CHANDHOK, Brennen MUELLER, Richard VREELAND
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Patent number: 11532558Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.Type: GrantFiled: September 27, 2019Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Carl Naylor, Mauro Kobrinsky, Richard Vreeland, Ramanan Chebiam, William Brezinski, Brennen Mueller, Jeffery Bielefeld
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Publication number: 20220336267Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: ApplicationFiled: June 27, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Patent number: 11404307Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: GrantFiled: September 27, 2019Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Patent number: 11367684Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.Type: GrantFiled: May 21, 2018Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Ehren Mannebach, Kevin Lin, Richard Vreeland
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Publication number: 20220181251Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Patent number: 11289421Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: GrantFiled: September 26, 2019Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20210098360Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Publication number: 20210098387Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Carl Naylor, Mauro Kobrinsky, Richard Vreeland, Ramanan Chebiam, William Brezinski, Brennen Mueller, Jeffery Bielefeld
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Publication number: 20210098359Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20210091194Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Inventors: Rami HOURANI, Richard VREELAND, Giselle ELBAZ, Manish CHANDHOK, Richard E. SCHENKER, Gurpreet SINGH, Florian GSTREIN, Nafees KABIR, Tristan A. TRONIC, Eungnak HAN
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Patent number: 10747708Abstract: A system for communicating between electronic devices on a communication bus includes a communication bus and one or more communication circuits each having an output driver coupled to the communication bus and each having an input terminal. Each communication circuit produces, in response to a request message, a data communication on the communication bus in a predetermined order with respect to data communications from other communication circuits so that the data communications from each communication circuit form a sequential data stream in response to the request message.Type: GrantFiled: March 8, 2018Date of Patent: August 18, 2020Assignee: Allegro MicroSystems, LLCInventors: Nevenka Kozomora, Richard Vreeland
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Publication number: 20190355665Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.Type: ApplicationFiled: May 21, 2018Publication date: November 21, 2019Inventors: Ehren MANNEBACH, Kevin LIN, Richard VREELAND
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Publication number: 20190278737Abstract: A system for communicating between electronic devices on a communication bus includes a communication bus and one or more communication circuits each having an output driver coupled to the communication bus and each having an input terminal. Each communication circuit produces, in response to a request message, a data communication on the communication bus in a predetermined order with respect to data communications from other communication circuits so that the data communications from each communication circuit form a sequential data stream in response to the request message.Type: ApplicationFiled: March 8, 2018Publication date: September 12, 2019Applicant: Allegro MicroSystems, LLCInventors: Nevenka Kozomora, Richard Vreeland
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Patent number: 9787495Abstract: A network slave device includes a transceiver for communicating over a communication bus in accordance with a point-to-point network protocol. The network slave device may include an address to identify the network slave device on the network. It may also include a communication circuit configured to process a command received by the transceiver and generate a reply for transmission over the communication bus if an address included in the command matches the address of the slave device. A master device communicating on the network may send commands including the address of the slave device in accordance with the point-to-point network protocol. In an embodiment, the point-to-point protocol is the SENT protocol.Type: GrantFiled: March 12, 2015Date of Patent: October 10, 2017Assignee: Allegro Microsystems, LLCInventors: Richard Vreeland, Nevenka Kozomora, Michael C. Doogue, Ricardo Scheinkerman
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Patent number: 9634715Abstract: A network slave device includes a transceiver for communicating over a communication bus in accordance with a point-to-point network protocol. The network slave device may have an address to identify the network slave device on the network. It may also have a communication circuit configured to process a series of commands received by the transceiver and respond to a command if a position of the command in the series of commands corresponds to the address of the network slave device. A master device communicating on the network may send the series of command in accordance with the point-to-point network protocol. In an embodiment, the point-to-point protocol is the SENT protocol.Type: GrantFiled: March 12, 2015Date of Patent: April 25, 2017Assignee: Allegro Microsystems, LLCInventors: Ricardo Scheinkerman, Nevenka Kozomora, Michael C. Doogue, Richard Vreeland