Patents by Inventor Richard Winterton

Richard Winterton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220413853
    Abstract: Systems, methods, and apparatuses to support packed data convolution instructions with shift control and width control are described.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: DEEPTI AGGARWAL, MICHAEL ESPIG, ROBERT VALENTINE, SUMIT MOHAN, PRAKARAM JOSHI, RICHARD WINTERTON
  • Publication number: 20220207154
    Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: Richard Winterton, Mohammad Reza Haghighat, Asit Mallick, Alaa Alameldeen, Abhishek Basak, Jason W. Brandt, Michael Chynoweth, Carlos Rozas, Scott Constable, Martin Dixon, Matthew Fernandez, Fangfei Liu, Francis McKeen, Joseph Nuzman, Gilles Pokam, Thomas Unterluggauer, Xiang Zou
  • Publication number: 20220113781
    Abstract: Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Jianwei Dai, Jianfang Zhu, Ivan Chen, Deepak Samuel Kirubakaran, Rajshree Chabukswar, Richard Winterton, Houfei Chen
  • Publication number: 20060140218
    Abstract: A method and system for adjusting a duty cycle to save power in a computing system is described. The system includes a network interface card (NIC) that has an active mode and a sleep mode. The NIC is coupled to an adjusting element that adjusts a duty cycle of the active time to the sleep time based at least in part on minimizing power consumption.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 29, 2006
    Inventor: Richard Winterton