Abstract: A two-stage transimpedance amplifier device having a transimpedance amplifier and a post-connected voltage differential amplifier. One of the two amplifiers receives a signal from the respective other amplifier as a reference signal. In this way, a noise compensation is able to be achieved.

Abstract: The invention relates to a method for detecting particles, having the steps of: receiving (S1) a measurement signal; calculating (S2) at least one estimated noise value using the received measurement signal; and detecting (S3) the particles using the measurement signal on the basis of at least one detection criterion, wherein the at least one detection criterion depends on the at least one calculated estimated noise value.

Abstract: The present invention provides methods and an apparatus for monitoring the optical output power of a laser diode (LD) having an associated photodiode (PD), and a particle sensor apparatus. The photodiode (PD) is operable together with the laser diode (LD), wherein it detects the light (LS) of the laser diode (LD) and converts it into an electrical current, and is thermally coupled to the laser diode (LD). Monitoring of the optical output power P is effected during the operation of the laser diode (LD) and is based on current measurements and/or voltage measurements at the laser diode (LD) and at the photodiode (PD).

Abstract: The invention relates to a method for detecting particles, having the steps of: receiving (S1) a measurement signal; calculating (S2) at least one estimated noise value using the received measurement signal; and detecting (S3) the particles using the measurement signal on the basis of at least one detection criterion, wherein the at least one detection criterion depends on the at least one calculated estimated noise value.

Abstract: The present invention provides methods and an apparatus for monitoring the optical output power of a laser diode (LD) having an associated photodiode (PD), and a particle sensor apparatus. The photodiode (PD) is operable together with the laser diode (LD), wherein it detects the light (LS) of the laser diode (LD) and converts it into an electrical current, and is thermally coupled to the laser diode (LD). Monitoring of the optical output power P is effected during the operation of the laser diode (LD) and is based on current measurements and/or voltage measurements at the laser diode (LD) and at the photodiode (PD).

Abstract: A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.

Abstract: A method of reading memory includes sensing a plurality of memory cells simultaneously and providing a data signal corresponding to one of a plurality of programming states. The plurality of programming states include a number of programming states equal to twice a number of memory cells in the plurality of memory cells. The data signal is processed, providing binary data representative of the data signal. The binary data includes a number of information bits equal to the number of memory cells.

Abstract: A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.

Abstract: A method of reading memory includes sensing a plurality of memory cells simultaneously and providing a data signal corresponding to one of a plurality of programming states. The plurality of programming states include a number of programming states equal to twice a number of memory cells in the plurality of memory cells. The data signal is processed, providing binary data representative of the data signal. The binary data includes a number of information bits equal to the number of memory cells.

Abstract: A device limits a capacitance charging current. The device has a differentiating device that is coupled in parallel with a capacitance that is to be charged at a charging node. A switching device is connected to an output of the differentiating device. The switching device prevents a charging current—which is supplied to the capacitor—if a predetermined value is applied to the output of the differentiating device.

Abstract: A method and arrangement are provided for programming an electrically erasable programmable read-only memory cell capable of storing at least one information bit. The memory cell has a charge-trapping region. According to the invention, during a first period of time, a fixed voltage is applied to the memory cell to inject and store electrical charge in the charge-trapping region. This period of time is followed by second period of time during which a constant current is applied to the memory cell to complete the programming step. By monitoring a change in voltage during the second period of time, a monitoring of a resulting threshold voltage is possible directly during programming.

Abstract: A cell arrangement comprising a memory cell arranged in parallel to a first capacitor is charged to a first voltage potential. A second capacitor is charged to a second voltage potential, which is higher than the first voltage potential. The second capacitor is connected to the cell arrangement while the voltage over the cell arrangement comprising the first capacitor is kept constant. The resulting current from the second capacitor through the memory cell is used to detect the state of the memory cell.

Abstract: An integrated circuit arrangement comprises at least one circuit to be controlled and a control logic for controlling the at least one circuit to be controlled. Furthermore, a switch is connected between the circuit to be controlled and the control logic. The switch is adapted to connect the control logic to the circuit to be controlled in a first switching state and a programmable controller to be at least one circuit to be controlled in a second switching state.

Abstract: A cell arrangement comprising a memory cell arranged in parallel to a first capacitor is charged to a first voltage potential. A second capacitor is charged to a second voltage potential, which is higher than the first voltage potential. The second capacitor is connected to the cell arrangement while the voltage over the cell arrangement comprising the first capacitor is kept constant. The resulting current from the second capacitor through the memory cell is used to detect the state of the memory cell.

Abstract: A method and arrangement are provided for programming an electrically erasable programmable read-only memory cell capable of storing at least one information bit. The memory cell has a charge-trapping region. According to the invention, during a first period of time, a fixed voltage is applied to the memory cell to inject and store electrical charge in the charge-trapping region. This period of time is followed by second period of time during which a constant current is applied to the memory cell to complete the programming step. By monitoring a change in voltage during the second period of time, a monitoring of a resulting threshold voltage is possible directly during programming.

Abstract: A method for sensing current conducted through a memory cell in which a memory cell current is supplied to, or drawn from, a first sensing node. The first sensing node is defined by a common connection point between the first terminal of a sensor element and an input of an inverting amplifier. A second sensing node is defined by a common connection point between a second terminal of the sensor element and the output of the inverting amplifier. The method further includes applying a reference potential to a reference input of the inverting amplifier, wherein the inverting amplifier is operable to apply substantially the reference potential to the first sensing node and to produce, in response, a sensor signal at the second sensing node, the sensor signal representative of the memory cell current supplied to, or drawn from, the first sensing node. Subsequently, the sensor signal is detected, and accordingly, the memory cell current supplied to, or drawn from the first sensing node can be ascertained.