Patents by Inventor Rishabh Mehandru

Rishabh Mehandru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896907
    Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Patrick H. Keys, Hei Kam, Rishabh Mehandru, Aaron A. Budrevich
  • Patent number: 10896963
    Abstract: Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Tahir Ghani, Szuya S. Liao
  • Patent number: 10892326
    Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
  • Patent number: 10886217
    Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru
  • Patent number: 10886272
    Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Rishabh Mehandru, Anupama Bowonder, Anand S. Murthy, Tahir Ghani
  • Publication number: 20200411430
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Rishabh MEHANDRU
  • Publication number: 20200411640
    Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Rishabh MEHANDRU, Stephen CEA, Anupama BOWONDER, Juhyung NAM, Willy RACHMADY
  • Publication number: 20200411644
    Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Aaron LILAK, Rishabh MEHANDRU, Willy RACHMADY, Harold KENNEL, Tahir GHANI
  • Publication number: 20200411690
    Abstract: An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Dax M. Crum, Cory E. Weber, Rishabh Mehandru, Harold Kennel, Benjamin Chu-Kung
  • Publication number: 20200403007
    Abstract: Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Nicholas THOMSON, Ayan KAR, Kalyan KOLLURU, Nathan JACK, Rui MA, Mark BOHR, Rishabh MEHANDRU, Halady Arpit RAO
  • Patent number: 10872820
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Bruce Block, Valluri R. Rao, Patrick Morrow, Rishabh Mehandru, Doug Ingerly, Kimin Jun, Kevin O'Brien, Paul Fischer, Szyua S. Liao
  • Patent number: 10872960
    Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Pratik A. Patel, Thomas T. Troeger, Szuya S. Liao
  • Patent number: 10861870
    Abstract: A semiconductor stacked device include a first plurality of device layers separated from one another by a first plurality of dielectric layers, a first electrically conductive via coupled to a contact portion of a device layer of the first plurality of the device layers, a second plurality of device layers separated from one another by a second plurality of dielectric layers, and a second electronically conductive via coupled to a contact portion of a device layer of the second plurality of the device layers. The first electronically conductive via extends to a frontside of the semiconductor stacked device and the second electrically conductive via extends to a backside of the semiconductor stacked device. The first plurality of device layers form a stair pattern in a first direction and the second plurality of device layers form a stair pattern in a second direction inverted from the first direction.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Morrow, Rishabh Mehandru
  • Publication number: 20200381525
    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
    Type: Application
    Filed: August 21, 2020
    Publication date: December 3, 2020
    Inventors: Patrick MORROW, Rishabh MEHANDRU, Aaron D. LILAK, Kimin JUN
  • Patent number: 10847635
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
  • Publication number: 20200335501
    Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.
    Type: Application
    Filed: March 2, 2018
    Publication date: October 22, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Cheng-ying Huang, Willy Rachmady, Aaron Lilak
  • Publication number: 20200312846
    Abstract: An integrated circuit includes: a germanium-containing fin structure above a layer of insulation material; a group III-V semiconductor material containing fin structure above the layer of insulation material; a first gate structure on a portion of the germanium-containing fin structure; a second gate structure on a portion of the group III-V semiconductor material containing fin structure; a first S/D region above the layer of insulation material and laterally adjacent to the portion of the germanium-containing fin structure, the first S/D region comprising a p-type impurity and at least one of silicon or germanium; a second S/D region above the layer of insulation material and laterally adjacent to the portion of the group III-V semiconductor material containing fin structure, the second S/D region comprising an n-type impurity and a second group III-V semiconductor material; and a layer comprising germanium between the layer of insulation material and the second S/D region.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 1, 2020
    Applicant: INTEL CORPORATION
    Inventors: Willy Rachmady, Abhishek A. Sharma, Ravi Pillarisetty, Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang
  • Patent number: 10790281
    Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Roza Kotlyar, Stephen M. Cea, Patrick H. Keys
  • Publication number: 20200303238
    Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Inventors: Ehren MANNEBACH, Aaron LILAK, Rishabh MEHANDRU, Hui Jae YOO, Patrick MORROW, Kevin LIN
  • Publication number: 20200303509
    Abstract: Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA