Patents by Inventor Rishi Bhooshan

Rishi Bhooshan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9494987
    Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.
    Type: Grant
    Filed: November 30, 2013
    Date of Patent: November 15, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dzung T. Tran, Rishi Bhooshan, Rakesh Pandey, Fujio Takeda
  • Patent number: 9455233
    Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh and an active wire mesh. The wire meshes can be formed in the same layer over the circuits to be protected or in different layers. The wire meshes also may cover the entire chip area or only predetermined areas, such as over secure memory and register areas. The wire meshes are connected to a tamper detection module, which monitors the meshes and any signals transmitted via the meshes to detect attempts to access the protected circuits via micro-probing.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: September 27, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rishi Bhooshan, Mohit Arora, Rakesh Pandey
  • Publication number: 20160163671
    Abstract: A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment.
    Type: Application
    Filed: December 3, 2014
    Publication date: June 9, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: SHAILESH KUMAR, Rishi Bhooshan, Chee Seng Foong, Vikas Garg, Navas Khan Oratti Kalandar, Chetan Verma
  • Patent number: 9337140
    Abstract: A semiconductor device includes a semiconductor die having opposing first and second main surfaces, contact pads and a metal ring accessible from the first main surface, and signal leads surrounding and spaced from the die. Each of the signal leads has a first end near the die, a second end remote from the die, and a body extending between the first and second ends. A dummy lead frame is disposed between the signal leads first ends and the die, and connected to a fixed potential. First bond wires are coupled to respective ones of the signal leads and the contact pads. Second, shield bond wires, located adjacent to respective ones of the bond wires, are coupled to the dummy lead frame and the metal ring.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: May 10, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shailesh Kumar, Rishi Bhooshan, Meng Kong Lye, Sumit Varshney, Chetan Verma
  • Publication number: 20150364439
    Abstract: A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Shailesh Kumar, Rishi Bhooshan, Vikas Garg, Chetan Verma, Navas Khan Oratti Kalandar
  • Patent number: 9196598
    Abstract: A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: November 24, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shailesh Kumar, Rishi Bhooshan, Vikas Garg, Chetan Verma, Navas Khan Oratti Kalandar
  • Patent number: 9147656
    Abstract: A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: September 29, 2015
    Assignee: FREESCALE SEMICONDUTOR, INC.
    Inventors: Sumit Varshney, Rishi Bhooshan, Meng Kong Lye, Chetan Verma
  • Publication number: 20150221592
    Abstract: A decoupling capacitor (decap) for circuitry (e.g., an I/O interface) in a semiconductor die is formed using one or more pairs of (parallel) bond wires wire-bonded to bond pads on a top surface of the die. Depending on the implementation, the pairs of bond wires may be horizontally or vertically aligned and may be bonded to I/O and/or array bond pads.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Inventors: Chetan Verma, Rishi Bhooshan, Vikas Garg, Shailesh Kumar, Navas Khan Oratti Kalandar
  • Publication number: 20150214167
    Abstract: A semiconductor die has elongate, adjacent external interface cells that form an interface cell row. Each of the external interface cells provides an external interface for a circuit node of the die. Bond pads are disposed on a surface of the die, with each of the bond pads being electrically connected to a directly underlying one of the interface cells of the interface cell row. Each of the bond pads has a longitudinal axis aligned with a lengthwise axis of its respective directly underlying interface cell. Each of the bond pads also has a multiple potential wire bond site locations along its respective longitudinal axes.
    Type: Application
    Filed: January 26, 2014
    Publication date: July 30, 2015
    Inventors: Rishi Bhooshan, Sachin Kalra, Rakesh Pandey, Dzung T. Tran
  • Publication number: 20150153811
    Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.
    Type: Application
    Filed: November 30, 2013
    Publication date: June 4, 2015
    Inventors: DZUNG T. TRAN, RISHI BHOOSHAN, RAKESH PANDEY, FUJIO TAKEDA
  • Publication number: 20140353849
    Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventors: Mohit Arora, Prashant Bhargava, Rishi Bhooshan
  • Patent number: 8896086
    Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohit Arora, Prashant Bhargava, Rishi Bhooshan
  • Publication number: 20140332811
    Abstract: A semiconductor die has an active face with an arrangement of I/O pads around its edges. The I/O pads include bond pads and probe pads. Two types of I/O pads are provided and the two types of pads are arranged in a staggered arrangement around the edges of the die. The first type of I/O pad has bond pads that are spaced from the probe pads and connected with an interconnecting member. The second type of I/O pads has bond pads that are adjacent to and abutting probe pads. Providing two types of I/O pads and the staggered arrangement of the I/O pads reduces the area of the I/O pads and underlying I/O regions, which saves core area of the die.
    Type: Application
    Filed: May 12, 2013
    Publication date: November 13, 2014
    Inventors: Naveen Kumar, Gurinder Singh Baghria, Rishi Bhooshan, Jesse Phou
  • Patent number: 7315992
    Abstract: Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of memory modules. One more feature enables determination of whether sufficient voltages will be applied to program efuses in a module containing the efuses. Yet another feature enables the signal characteristics of an output path/pin to be determined to check for any EM violations.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: January 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Rishi Bhooshan, Sampath Kuve, Venugopal Puvvada
  • Publication number: 20070094630
    Abstract: An aspect of the present invention computationally determines the metal density of each metal layer supporting a power grid structure providing power to the elements of an integrated circuits. The metal densities are computed such that the power grid would support aggregate power and IR drop constraints. The metal densities thus computed are provided as inputs to a router block, which places the grid structure along with the signal paths on the layout of the eventual integrated circuit sought to be fabricated. Due to the computation of the metal densities upfront and providing to the router block, the iterative design of the IC might be avoided.
    Type: Application
    Filed: October 21, 2005
    Publication date: April 26, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rishi Bhooshan
  • Publication number: 20060026540
    Abstract: Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of memory modules. One more feature enables determination of whether sufficient voltages will be applied to program efuses in a module containing the efuses. Yet another feature enables the signal characteristics of an output path/pin to be determined to check for any EM violations.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rishi BHOOSHAN, Sampath KUVE, Venugopal PUVVADA