Abstract: Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

Abstract: A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

Abstract: Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

Abstract: Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighboring blocks and the I/O channels.

Abstract: A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

Abstract: Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighoring blocks and the I/O channels.

Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh and an active wire mesh. The wire meshes can be formed in the same layer over the circuits to be protected or in different layers. The wire meshes also may cover the entire chip area or only predetermined areas, such as over secure memory and register areas. The wire meshes are connected to a tamper detection module, which monitors the meshes and any signals transmitted via the meshes to detect attempts to access the protected circuits via micro-probing.

Abstract: A surface-mounted integrated circuit package containing a semiconductor die has at least two conductive plates on its lower surface for contacting power and ground areas of a printed circuit board (PCB). The conductive plates are electrically connected to metal studs encapsulated within the package and which link the plates to the power and ground grids of the semiconductor die. Power and ground can thus be provided to the package with conductive patterns on the PCB that match with the plates. The resistance of the plates is low and hence the IR drop across the die is low. By supplying power directly to the package via the plates, the peripheral package pins that would otherwise have been allocated for power (and ground) are now freed up for signal assignment.

Abstract: A semiconductor device includes a semiconductor die having opposing first and second main surfaces, contact pads and a metal ring accessible from the first main surface, and signal leads surrounding and spaced from the die. Each of the signal leads has a first end near the die, a second end remote from the die, and a body extending between the first and second ends. A dummy lead frame is disposed between the signal leads first ends and the die, and connected to a fixed potential. First bond wires are coupled to respective ones of the signal leads and the contact pads. Second, shield bond wires, located adjacent to respective ones of the bond wires, are coupled to the dummy lead frame and the metal ring.

Abstract: A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.

Abstract: A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.

Abstract: A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.

Abstract: A decoupling capacitor (decap) for circuitry (e.g., an I/O interface) in a semiconductor die is formed using one or more pairs of (parallel) bond wires wire-bonded to bond pads on a top surface of the die. Depending on the implementation, the pairs of bond wires may be horizontally or vertically aligned and may be bonded to I/O and/or array bond pads.

Abstract: A semiconductor die has elongate, adjacent external interface cells that form an interface cell row. Each of the external interface cells provides an external interface for a circuit node of the die. Bond pads are disposed on a surface of the die, with each of the bond pads being electrically connected to a directly underlying one of the interface cells of the interface cell row. Each of the bond pads has a longitudinal axis aligned with a lengthwise axis of its respective directly underlying interface cell. Each of the bond pads also has a multiple potential wire bond site locations along its respective longitudinal axes.

Abstract: An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

Abstract: A semiconductor die has an active face with an arrangement of I/O pads around its edges. The I/O pads include bond pads and probe pads. Two types of I/O pads are provided and the two types of pads are arranged in a staggered arrangement around the edges of the die. The first type of I/O pad has bond pads that are spaced from the probe pads and connected with an interconnecting member. The second type of I/O pads has bond pads that are adjacent to and abutting probe pads. Providing two types of I/O pads and the staggered arrangement of the I/O pads reduces the area of the I/O pads and underlying I/O regions, which saves core area of the die.

Abstract: Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of memory modules. One more feature enables determination of whether sufficient voltages will be applied to program efuses in a module containing the efuses. Yet another feature enables the signal characteristics of an output path/pin to be determined to check for any EM violations.