Abstract: The amount of jitter incurred when reading data written into a FIFO can be reduced by clocking the FIFO with Read Clock pulses at a frequency xfn where x is a whole integer and fn is the frequency at which the memory is clocked to write data. Read Addresses are applied to the FIFO at a frequency on the order of fn to identify successive locations in the memory for reading when the memory is clocked with read clocked pulses to enable reading of samples stored at such successive locations. The duration of at least one successive Read Addresses is altered in response to memory usage status to maintain memory capacity below a prescribed threshold.

Abstract: To achieve improved jitter performance within prescribed bandwidth constraints, a receiver (140) samples a digital signal (11) upon each of n periodic sample clock pulses that occur during the interval t, where n is chosen such that log2(n+1) is an integer (x) greater than zero. At the each of each interval t, the receiver generates a x+1-bit sample value having a first bit indicating the value of the digital signal being sampled, and x remaining bits which collectively indicate a sample interval during which the digital signal changed states if such a change did occur When a change does occur, the receiver inverts the first bit of each sample value upon decoding to coincide with the change in the digital signal.

Abstract: To achieve improved jitter performance within prescribed bandwidth constraints, a receiver (140) samples a digital signal (11) upon each of n periodic sample clock pulses that occur during the interval t, where n is chosen such that log2(n+1) is an integer (x) greater than zero. At the each of each interval t, the receiver generates a x+1-bit sample value having a first bit indicating the value of the digital signal being sampled, and x remaining bits which collectively indicate a sample interval during which the digital signal changed states if such a change did occur When a change does occur, the receiver inverts the first bit of each sample value upon decoding to coincide with the change in the digital signal.