Abstract: N key generation circuits are arranged in a pipeline having N stages. Each key generation circuit is configured to generate a round key as a function of a respective input key and a respective round constant. Output signal lines that carry the round key from a key generation circuit in a stage of the pipeline, except the key generation circuit in a last stage of the pipeline, are coupled to the key generation circuit in a successive stage of the pipeline to provide the respective input key.

Abstract: Data exchange between a memory mapped interface and a streaming interface may include receiving sub-packets of a packet from a first interface, storing the sub-packets within a memory at addresses determined according to a ratio of a width of the first interface and a width of a second interface, and determining occupancy, of the memory as the sub-packets are stored. Responsive to determining that the occupancy of the memory meets a trigger level, sub-packets may be read from the memory at addresses determined according to the ratio and sending the sub-packets using the second interface.

Abstract: The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

Abstract: A method of processing data within a controller for a network can include, while frame lock is not established, detecting a first preamble and a second preamble within a data stream of the network (1210, 1235). Biphase units between the first preamble and the second preamble can be counted (1215). Frame lock can be acquired on the data stream responsive to determining that the first preamble and the second preamble are separated by a number of biphase units corresponding to a frame (1235). A synchronization signal indicating that frame lock has been acquired can be output responsive to acquiring frame lock on the data stream (1240).

Abstract: A method of processing data within a controller for a network can include identifying frames within a data stream within the network (1110) and detecting a deadlock state according to a number of consecutive frames comprising at least one set control bit (1130). The method can include, responsive to detecting the deadlock state, adjusting the at least one control bit within a current frame (1135). Adjusting the at least one control bit clears the deadlock state and generates a modified frame. The modified frame can be output to at least one node within the network (1140).