Patents by Inventor Robert Bogdan Staszewski

Robert Bogdan Staszewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11177810
    Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 16, 2021
    Inventors: Feng Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Publication number: 20210336583
    Abstract: The disclosure relates to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit being configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit being configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.
    Type: Application
    Filed: May 12, 2021
    Publication date: October 28, 2021
    Inventors: Mina SHAHMOHAMMADI, Masoud BABAIE, Robert Bogdan STASZEWSKI
  • Publication number: 20210313931
    Abstract: The invention relates to a resonator circuit, the resonator circuit comprising a transformer comprising a primary winding and a secondary winding, wherein the primary winding is inductively coupled with the secondary winding, a primary capacitor being connected to the primary winding, the primary capacitor and the primary winding forming a primary circuit, and a secondary capacitor being connected to the secondary winding, the secondary capacitor and the secondary winding forming a secondary circuit, wherein the resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 7, 2021
    Inventors: Mina SHAHMOHAMMADI, Masoud BABAIE, Robert Bogdan STASZEWSKI
  • Patent number: 11139778
    Abstract: Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chieh Li, Robert Bogdan Staszewski
  • Publication number: 20210305940
    Abstract: Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: Chao-Chieh LI, Robert Bogdan STASZEWSKI
  • Publication number: 20210242873
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 5, 2021
    Inventors: CHIA-CHUN LIAO, MIN-SHUEH YUAN, CHAO-CHIEH LI, ROBERT BOGDAN STASZEWSKI
  • Publication number: 20210234517
    Abstract: Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Feng-Wei KUO, Kai XU, Robert Bogdan STASZEWSKI
  • Publication number: 20210184681
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 17, 2021
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Patent number: 11031942
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 11025198
    Abstract: The invention relates to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit being configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit being configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 1, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski
  • Patent number: 11025197
    Abstract: The invention relates to a resonator circuit, the resonator circuit comprising a transformer comprising a primary winding and a secondary winding, wherein the primary winding is inductively coupled with the secondary winding, a primary capacitor being connected to the primary winding, the primary capacitor and the primary winding forming a primary circuit, and a secondary capacitor being connected to the secondary winding, the secondary capacitor and the secondary winding forming a secondary circuit, wherein the resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 1, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski
  • Patent number: 10992302
    Abstract: A waveform synthesizer comprises a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input. The waveform detector is arranged to sample said waveform in response to said reference input and to determine waveform information about said oscillator. The waveform information is operative to adjust said controllable oscillator.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 27, 2021
    Assignee: UNIVERSITY COLLEGE DUBLIN, NATIONAL UNIVERSITY OF IRELAND
    Inventors: Teerachot Siriburanon, Vivek Govindaraj, Robert Bogdan Staszewski
  • Patent number: 10985709
    Abstract: Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei Kuo, Kai Xu, Robert Bogdan Staszewski
  • Publication number: 20210091770
    Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei KUO, Chewn-Pu JOU, Huan-Neng CHEN, Lan-Chou CHO, Robert Bogdan STASZEWSKI, Seyednaser POURMOUSAVIAN
  • Patent number: 10931285
    Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao Chieh Li, Min-Shueh Yuan, Robert Bogdan Staszewski, Chia-Chun Liao
  • Patent number: 10903798
    Abstract: A novel and useful noise reduction technique that improves the noise figure (NF) of a common-source (CS) low noise amplifier (LNA). The technique exploits dc current reuse and increases transconductance of the CS transistor while maintaining its power consumption. By using noise reduction and dc current reuse techniques, the thermal current noise of the noise cancellation stage is reduced without adding any extra branch to the circuit. As a result, the current thermal noise of second stage decreases dramatically leading to better NF without consuming any extra power. Moreover, since the circuit block is implemented using a pMOS transistor, the second order nonlinearity of pMOS and nMOS transistors cancel each other, resulting in improved nonlinearity performance of the LNA, including improvements to both IIP2 and IIP3.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Short Circuit Technologies LLC
    Inventors: Amirhossein Ansari Bozorg, Robert Bogdan Staszewski
  • Patent number: 10868542
    Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Robert Bogdan Staszewski
  • Patent number: 10862486
    Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 8, 2020
    Inventors: Feng Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Robert Bogdan Staszewski, Seyednaser Pourmousavian
  • Patent number: 10862423
    Abstract: A novel and useful mm-wave frequency generation system is disclosed that takes advantage of injection locking techniques to generate an output oscillator signal with improved phase noise (PN) performance and power efficiency. Low frequency and high frequency DCOs as well as a pulse generator make up the oscillator system. A fundamental low frequency (e.g., 30 GHz) signal and its sufficiently strong higher (e.g., fifth) harmonic (e.g., 150 GHz) are generated simultaneously in a single oscillator system. The second high frequency DCO having normally poor phase noise is injected locked to the first low frequency DCO having good phase noise. Due to injection locking, the high frequency output signal generated by the second DCO exhibits good phase noise since the phase noise of the second DCO tracks that of the first DCO.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: December 8, 2020
    Assignee: UNIVERSITY COLLEGE DUBLIN
    Inventors: Amirhossein Ansari Bozorg, Robert Bogdan Staszewski
  • Patent number: 10862426
    Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Chieh Li, Robert Bogdan Staszewski